• ETRI Journal
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• v.36 no.4
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• pp.635-642
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• 2014

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.45-61
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• 1999

General trend in electronics industry towards multimedia in the 21 century is presented here. All equipments require fast graphic processing together with thin and lightweight assembly technology. In Japan, CSP was developed and applied to mobile equipments for several years, and recently stacked die assembly technology is being developed. In addition, so-called flip chip technology is also being developed and which is applied to MCP and MCM little by little these days. Here current packaging technology in Japan is presented including above.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.69-74
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• 2019

The aim of this work is to investigate the effect of the microtip length in a slot-die head on coating of a fine poly(3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) (PEDOT:PSS) stripe. To this end, we have employed a meniscus guide with a 150-㎛-wide microtip and performed roll-to-roll slot-die coatings by varying its length between 500 ㎛ and 50 ㎛. When the microtip length is 150 ㎛ or shorter, we have observed three unexpected phenomena; 1) though the solution spreads much wider than the microtip width, yet the coated stripe width is almost the same as the microtip width, 2) the stripe width decreases, but the stripe thickness is rather increased with increasing coating speed at a fixed flow rate, 3) we obtain stripes much narrower than the microtip width at high coating speeds. It is due to the fact that 1) the meniscus is not well controlled by a short microtip, 2) the main stream of solution from the outlet is very close to the substrate and thus the distributed solution along the head lip merges with the main stream, and 3) the solution is not spread over the entire microtip end at high coating speeds, causing a tiny wobble in the meniscus. Using the 150-㎛-wide and 250-㎛-long microtip, we have fabricated 153-㎛-wide and 94-nm-thick PEDOT:PSS stripe at the maximum coating speed of 13 mm/s. To demonstrate its applicability in solution-processable organic light-emitting diodes (OLEDs), we have also fabricated an OLED device with the fine PEDOT:PSS stripe and obtained strong light emission from it.

• Journal of the Semiconductor & Display Technology
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• v.20 no.1
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• pp.70-76
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• 2021

A cylindrical microlens (CML) has been widely used as an optical element for organic light-emitting diodes (OLEDs), light diffusers, image sensors, 3D imaging, etc. To fabricate high-performance optoelectronic devices, the CML with high aspect ratio is demanded. In this work, we report on facile solution-based processes (i.e., slot-die and needle coatings) to fabricate the CML using poly(methyl methacrylate) (PMMA). It is found that compared with needle coating, slot-die coating provides the CML with lower aspect ratio due to the wide spread of solution along the hydrophilic head lip. Although needle coating provides the CML with high aspect ratio, it requires a high precision needle array module. To demonstrate that the aspect ratio of CML can be enhanced using slot-die coating, we have varied the molecular weight of PMMA. We can achieve the CML with higher aspect ratio using PMMA with lower molecular weight at a fixed viscosity because of the higher concentration of PMMA solute in the solution. We have also shown that the aspect ratio of CML can be further boosted by coating it repeatedly. With this scheme, we have fabricated the CML with the width of 252 ㎛ and the thickness of 5.95 ㎛ (aspect ratio=0.024). To visualize its light diffusion property, we have irradiated a laser beam to the CML and observed that the laser beam spreads widely in the vertical direction of the CML.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.32-37
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• 2023

For the potential applications in large-area OLED lightings, hydrogen fuel cells, and secondary batteries, we have performed an intermittent coating of high-viscosity polydimethylsiloxane using roll-to-roll slot die coater. During intermittent coating, dead zones inevitably appear where the thickness of PDMS patch films becomes non-uniform, especially at the leading/trailing edge. To reduce it, we have coated the PDMS patches by varying the process parameters such as the installation angle of the slot die head, coating speed, and patch interval. It is observed that the PDMS solution flows down and thus the thickness profile is non-uniform for horizonal intermittent coating, whereas the PDMS solution remaining on the head lip causes an increase in the PDMS thickness at the leading/trailing edges for vertical intermittent coating when the coating velocity is low. As the coating speed increases, however, the dead zone is shown to be reduced. It is addressed that the overall dead zone (the dead zone at the leading edge + the dead zone at the trailing edge) is smaller with horizontal intermittent coating than with vertical intermittent coating.

• Korean Journal of Metals and Materials
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• v.48 no.4
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• pp.363-368
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• 2010

N,N'-diphenyl-N,N'-bis(3-methylphenyl)1-1' biphenyl-4,4'-diamine (TPD) hole-transporting layers were deposited using a continuous slot-die coating method on ITO/PET flexible substrates. It is crucial that the substrates have a very smooth surface with a RMS roughness of less than 2 nm for the deposition of semiconductor nanocrystals or Quantum Dots. The parameters of the slot-die coating, including the solution concentration of the TPD, the gap between the slot-die and the substrates, and the coating speed were controlled in these experiments. To obtain full coverage of the TPD films on the ITO/PET substrates (40 mm wide and several meters long), the injection rates of the TPD solution were increased proportional to the coating speed of the flexible substrates. Additionally, the injection rates must be increased as the gap distance changes from 400 to 600 ${\mu}m$ at the same coating speed. A RMS surface roughness of less than 2 nm was obtained, in contrast to bare ITO/PET substrates, at 13 nm, as the coating speed and gap distance increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.30-36
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical bus across memory layers are implemented by many semiconductor companies. 3D memories are composed of known-good-dies (KGDs). If additional faults are arisen during bonding, they should be repaired. In order to enhance the yield of 3D memories with inter-die redundancies, a die-matching method is needed to effectively stack memory dies in a 3D memory. In this paper, a new die-matching method is proposed for 3D memory yield enhancement with inter-die redundancies considering additional faults arisen during bonding. Three boundary-limited conditions are used in the proposed die-matching method; they set bounds to the search spaces for selecting memory dies to manufacture a 3D memory. Simulation results show that the proposed die-matching method can greatly enhance the 3D memory yield.

• Journal of the Korea Society for Simulation
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• v.19 no.1
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• pp.1-11
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• 2010

K company produces semiconductor package products under the make-to-order policy to supply for domestic and foreign semiconductor manufacturing companies. Its production process is a machine-paced assembly line type, which consists of die sawing, assembly, and test. This paper suggests three plans to increase process throughput based on the process analysis of K company and evaluates them via a simulation model using a real data collected. The three plans are line balancing by adding machines to the bottleneck process, product group scheduling, and reallocation of the operators in non-bottleneck processes. The evaluation result shows the highest daily throughput increase of 17.3% with an effect of 2.8% reduction of due date violation when the three plans are applied together. Payback period for the mixed application of the three plans is obtained as 1.37 years.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.657-658
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• 2013

• Design & Manufacturing
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• v.10 no.3
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• pp.1-7
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• 2016

In the semiconductor industry the memory and chip were developed to high density memory and high performance chip, so circuit design was also high integrated and the test bed was needed to be thin and fine pitch socket. LGA(Land Grid Array) IC socket with thin wall thickness was designed to satisfy this requirement. The LGA IC socket plastic part was manufacture by injection molding process, it was needed accuracy, stiffness and suit resin with high flowability. After injection molding process the side gates were needed to remove for further assembly process. ln this study, the cold press cutting process was applied to remove the gates. For design of punch and die, the cold press cutting analysis was implemented by$DEFORM-2D^{TM}$ ln consideration of the simulation results, an adequate punch and die was designed and made for the cutting unit. In order to verify the performance of cutting process, the roughness of cutting section of the part was measured and was satisfied in requirement.