• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• Design & Manufacturing
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• 제14권3호
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• pp.63-70
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• 2020

As the consumer market in the VR(virtual reality) and the head-up display industry grows, the demand for 5-axis machines and grooving machines using on a ultra-precision machining increasing. In this paper, ultra-precision diamond tools satisfying the cutting edge width of 500 nm were developed through the process research of a focused ion beam. The material used in the experiment was a single-crystal diamond tool (SCD), and the equipment for machining the SCD used a focused ion beam. In order to reduce the influence of the Gaussian beam emitted from the focused ion beam, the lift-off process technology used in the semiconductor process was used. 2.9 ㎛ of Pt was coated on the surface of the diamond tool. The sub-micron tool with a cutting edge of 492.19 nm was manufactured through focused ion beam machining technology. Toshiba ULG-100C(H3) equipment was used to process fine-pattern using the manufactured ultra-precision diamond tool. The ultra-precision machining experiment was conducted according to the machining direction, and fine burrs were generated in the pattern in the forward direction. However, no burr occurred during reverse machining. The width of the processed pattern was 480 nm and the price of the pitch was confirmed to be 1 ㎛ As a result of machining.

• Design & Manufacturing
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• 제14권3호
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• pp.23-30
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• 2020

Laser Assisted Thermo-Compression Bonding (LATCB) has been proposed to improve the "chip tilt due to the difference in solder bump height" that occurs during the conventional semiconductor chip bonding process. The bonding module of the LATCB system has used a piezoelectric actuator to control the inclination of the compression jig on a micro scale, and the piezoelectric actuator has been directly coupled to the compression jig to minimize the assembly tolerance of the compression jig. However, this structure generates a lateral force in the piezoelectric actuator when the compression jig is tilted, and the stacked piezoelectric element vulnerable to the lateral force has a risk of failure. In this paper, the optimal design of the flexure hinge was performed to minimize the lateral force generated in the piezoelectric actuator when the compression jig is tilted by using the displacement difference of the piezoelectric actuator in the bonding module for LATCB. The design variables of the flexure hinge were defined as the hinge height, the minimum diameter, and the notch radius. And the effect of the change of each variable on the stress generated in the flexible hinge and the lateral force acting on the piezoelectric actuator was analyzed. Also, optimization was carried out using commercial structural analysis software. As a result, when the displacement difference between the piezoelectric actuators is the maximum (90um), the maximum stress generated in the flexible hinge is 11.5% of the elastic limit of the hinge material, and the lateral force acting on the piezoelectric actuator is less than 1N.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.274-286
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• 2016

This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using $0.13-{\mu}m$ CMOS technology and the die area is $4.2mm^2$. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.

• 한국정보전자통신기술학회논문지
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• 제11권2호
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• pp.189-194
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• 2018

현재 대부분의 집적회로는 bulk CMOS 기술을 사용해서 제작되고 있으나 전력 소모를 낮추고 die 크기를 줄이기에는 한계점에 도달해있다. 이러한 어려움을 획기적으로 극복할 수 있는 초저전력 기술로서 SOI CMOS 기술이 최근에 크게 각광을 받고 있다. 본 논문에서는 100 nm Thin SOI 기판 위에 제작된 n-채널 MOSFET 소자들의 열전자 효과들의 온도 의존성에 관한 연구 결과들이 논의되었다. 소자들이 LDD 구조를 갖고 있음에도 불구하고 열전자 효과들이 예상보다 더 심각한 것으로 나타났는데, 이는 채널과 기판 접지 사이의 직렬 저항이 크기 때문인 것으로 믿어졌다. 온도가 높을수록 채널에서의 phonon scattering의 증가와 함께 열전자 효과는 감소하였는데, 이는 phonon scattering의 증가는 결과적으로 열전자의 생성을 감소시켰기 때문인 것으로 판단된다.

• 마이크로전자및패키징학회지
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• 제16권4호
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• pp.1-4
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• 2009

본 연구에서는 실리콘 웨이퍼에 2중 다이싱 공정의 적용이 리드-온-칩 패키지로 조립되는 반도체 디바이스의 T.C. ($-65^{\circ}C$에서 $150^{\circ}C$까지의 온도변화에 지배되는 신뢰성 실험) 신뢰성에 어떠한 영향을 미치는 지를 보여준다. 기존 싱글 다이싱 공정은 웨이퍼에서 분리된 디바이스의 테두리 부위가 다이싱으로 인해 기계적으로 손상되는 결과를 보였으나, 2중 다이싱 공정은 분리된 디바이스의 테두리 부위가 거의 손상되지 않고 보존되는 것을 확인할 수 있었다. 이는 2중 다이싱의 경우 다이싱 동안 웨이퍼의 전면에 도입된 노치부위가 선택적으로 파손되면서 분리된 디바이스의 테두리 부위를 보호하기 때문으로 해석된다. 온도변화 실험을 통해 2중 다이싱 공정의 도입이 단일 다이싱 공정에 비해 T.C. 신뢰성에서도 대단히 좋은 결과를 보인다는 것을 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.98-107
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• 2013

This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of $2V_{P-P}$ using a single on-chip reference of $1V_{P-P}$. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 $mm^2$ consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.

• Design & Manufacturing
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• 제15권3호
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• pp.56-61
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• 2021

The increase in automation facilities in the injection molding industry is a very important process control item. The most important item when constructing an unmanned machine using a take-out robot is the "mold opening stroke" of the mold. The injection molding machine control method is divided into hydraulic type and electric type, and there have been few studies on the mold opening distance according to the control method. In this study, the correlation was confirmed by increasing the injection speed to 20, 50, 80, and 100% for the three types of hydraulic control method, open loop and close loop, and electric control method. Through the experiment, the following results were obtained. (1) It can be seen that the reproducibility is excellent with the electric, close loop, and open loop control methods. (2) When the injection speed is set to 50%, the mold opening distance is 263.10~263.27 mm, which is the most reproducible. (3) As a result of ANOVA, both injection speed and mold opening distance showed a significant difference in the hydraulic control method (p<0.05), but it was verified through experiments that there was no significant difference in the electric control method. Based on these results, when electric control is selected rather than hydraulic control, the reproducibility of the mold opening distance is excellent, so it is thought that the taking-out robot can take the object out of the mold more safely.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.