• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.136-145
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• 2006

Two major processing technologies of GaAs HBT and pHEMT have been released in production at Win Semiconductors corp. to address the strong demands of power amplifiers and switches for both handset and WLAN communications markets. Excellent performance with low processing cost and die shrinkage features is reported from the manufactured MMICs. With the stringent tighter manufacturing quality control WIN has successfully become one of the major pure open foundry house to serve the communication industries. The advancing of both technologies to include E/D-pHEMTs and BiHEMTs likes for multifunctional integration of PA, LNA, switch and logics is also highlighted.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.78-81
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• 2003

Polishing Processes are widely used in the glass, optical, die and semiconductor industry and are conventionally carried out using abrasive slurry and a polishing pad. But abrasive slurry process has a weak point that is high cost of handling of used slurry and hard controllability of slurry. Recently, some researches have attempted to solve these problems and one method is the development of a fixed abrasive pad. FAP has a couple of advantages including clean environment, lower CoC, easy controllability and higher form accuracy. But FAP also has a weak point that is need of dressing because of glazing and loading. The paper introduces the basic concept and fabrication technique of FAP using hydrophilic polymers with swelling characteristics in water and explains the self-conditioning phenomenon. Experimental results demonstrate to achieve nano surface roughness of soda lime glass for optical application

• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 춘계학술대회논문집A
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• pp.873-878
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• 2000

Semiconductor packaging technology is changed rapidly according to the trends of the micro miniaturization of multimedia and information equipment. For I/O limitation and fine pitch limitation, DIP and SOP/QFP are replaced by BGA/CSP. This is one of the surface mount technology(SMT). Solder ball is bumped n the die pad and connected onto mounting board. In ball bump formation, vacuum suction type ball alignment process is widely used, However this type has some problems such as ionization, static electricity and difficulty of fifo(first-input first-out) of solder balls. Seesaw type is reducing these problems and has a structural simplicity and economic efficiency. Ball cartridge velocity and ball aligned plate angle are Important variables to improve the ball alignment Process. In this paper, seesaw-type CSP solder ball loader is developed and the optimal velocity and plate angle are proposed.

• 산업경영시스템학회지
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• 제35권4호
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• pp.1-9
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• 2012

Decisions on reliability screening rules and burn-in policies are determined based on the estimated reliability. The variability in a semiconductor manufacturing process does not only causes quality problems but it also makes reliability estimation more complicated. This study investigates the nonuniformity characteristics of integrated circuit reliability according to defect density distribution within a wafer and between wafers then develops optimal burn-in policy based on the estimated reliability. New reliability estimation model based on yield information is developed using a spatial stochastic process. Spatial defect density variation is reflected in the reliability estimation, and the defect densities of each die location are considered as input variables of the burn-in optimization. Reliability screening and optimal burn-in policy subject to the burn-in cost minimization is examined, and numerical experiments are conducted.

• ETRI Journal
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• 제36권4호
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.145-151
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• 2013

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• 한국정밀공학회지
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• 제21권5호
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• pp.32-37
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• 2004

Polishing processes are widely used in the glass, optical, die and semiconductor industries. Chemical Mechanical Polishing (CMP) especially is becoming one of the most important ULSI processes for the 0.25m generation and beyond. CMP is conventionally carried out using abrasive slurry and a polishing pad. But the surface of the pad has irregular pores, so there is non-uniformity of slurry flow and of contact area between wafer and the pad, and glazing occurs on the surface of the pad. This paper introduces the basic concept and fabrication technique of the next generation CMP pad using micro-molding method to obtain uniform protrusions and pores on the pad surface.

• 응용통계연구
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• 제35권3호
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• pp.407-419
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• 2022

반도체는 제조 공정이 복잡하고 길어 결함이 발생될 때 빠른 탐지와 조치가 이뤄져야 결함으로 인한 손실을 최소화할 수 있다. 테스트 공정을 거쳐 구성된 웨이퍼 빈 맵(WBM)의 체계적인 패턴을 탐지하고 분류함으로써 문제의 원인을 유추할 수 있다. 이 작업은 수작업으로 이뤄지기 때문에 대량의 웨이퍼를 단 시간에 처리하는 데 한계가 있다. 본 논문은 웨이퍼 빈 맵의 정상 여부를 구분하기 위해 계층적 군집 분석을 활용한 새로운 결함 패턴 탐지 방법을 제시한다. 제시하는 방법은 여러 장점이 있다. 군집의 수를 알 필요가 없으며 군집분석의 조율 모수가 적고 직관적이다. 동일한 크기의 웨이퍼와 다이(die)에서는 동일한 조율 모수를 가지므로 대량의 웨이퍼도 빠르게 결함을 탐지할 수 있다. 소량의 결함 데이터만 있어도 그리고 데이터의 결함비율을 가정하지 않더라도 기계학습 모형을 훈련할 수 있다. 제조 특성상 결함 데이터는 구하기 어렵고 결함의 비율이 수시로 바뀔 수 있기 때문에 필요하다. 또한 신규 패턴 발생시에도 안정적으로 탐지한다. 대만 반도체 기업에서 공개한 실제 웨이퍼 빈 맵 데이터(WM-811K)로 실험하였다. 계층적 군집 분석을 이용한 결함 패턴탐지는 불량의 재현율이 96.31%로 기존의 공간 필터(spatial filter)보다 우수함을 보여준다. 결함 분류는 혼합 유형에 장점이 있는 계층적 군집 분석을 그대로 사용한다. 직선형과 곡선형의 긁힘(scratch) 결함의 특징에 각각 주성분 분석의 고유값과 2차 다항식의 결정계수를 이용하고 랜덤 포레스트 분류기를 이용한다.

• Design & Manufacturing
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• 제14권2호
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• pp.56-61
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• 2020

Recently, research for machining next-generation micro semiconductor processes and micro patterns has been actively conducted. In particular, it is applied to various industrial fields depending on the machining method in the case of FIB (Focused ion beam) milling. In this study, intends to deal with FIB milling machining technology for ultra-precision diamond tool fabrication technology. Ultra-precision diamond tools require nano-scale precision, and FIB milling is a useful method for nano-scale precision machining. However, FIB milling has a problem of Gaussian characteristics that are differently formed according to the beam current due to the input of an ion beam source, and there are process conditions to be considered, such as a side clearance angle problem of a diamond tool that is differently formed according to the tilting angle. A series of process steps for fabrication a ultra-precision diamond tool were studied and analyzed for each process. It was confirmed that the effect on the fabrication process was large depending on the spot size of the beam and the current of the beam as a result of the experimental analysis.