• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.96-96
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• 2007

Low voltage organic TFTs (OTFTs) and ZnO based TFTs (<5V), utilizing room temperature deposited $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin films were recently reported, pointing to high-k gate insulators as a promising route for realizing low voltage operating flexible electronics. $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin film is one of the most promising materials for gate insulator because of its large dielectric constant (~60) at room temperature. However their tendency to suffer from relatively high leakage current at low electric field (>0.3MV/cm) hinder the application of BZN thin films for gate insulator. In order to improve leakage current characteristics of BZN thin film, we mixed 30mol% MgO with 70mol% BZN and their dielectric and electric properties were characterized. We fabricated field-effect transistors with transparent oxide semiconductor ZnO serving as the electron channel and high-k $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ as the gate insulator. The devices exhibited low operation voltages (<4V) due to high capacitance of the $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ dielectric.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.6
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• pp.445-449
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• 2020

Non-volatile memory is approaching its fundamental limits with the Si₃N₄ storage layer, necessitating the use of alternative materials to achieve a higher programming/erasing speed, larger storage window, and better data retention at lower operating voltage. This limitation has restricted the development of the charge-trap memory, but can be addressed by using high-k dielectrics. The paper reviews the doping of nitrogen, titanium, and yttrium on high-k dielectrics as a storage layer by comparing MONOS devices with different storage layers. The results show that nitrogen doping increases the storage window of the Gd₂O₃ storage layer and improves its charge retention. Titanium doping can increase the charge capture rate of HfO₂ storage layer. Yttrium doping increases the storage window of the BaTiO₃ storage layer and improves its fatigue characteristics. Parameters such as the dielectric constant, leakage current, and speed of the memory device can be controlled by maintaining a suitable amount of external impurities in the device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.392-395
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• 2003

For the purpose of digital x-ray imaging, many materials such as $PbI_2$, $HgI_2$, TlBr, CdTe and CdZnTe have been under development for servaral years as direct converter layer. $Hgl_2$ film detector have recently been shown as one of the most promising semiconductor materials to be used as direct converters in x-ray digital radiography. This paper, the $HgI_2$ films are deposited on conductive-coated glass by screen printing, in which $HgI_2$ powder is embedded in a binder and solvent, and the slurry is used to coat the conductive-coated glass. We investigated electrical characteristic of the fabricated $HgI_2$ films. The x-ray response to radiological x-ray generator of 70Kvp using the current integration mode will be reported for screen printing films. These results indicate that $HgI_2$ detectors have high potential as new digital x-ray imaging devices for radiography.

• Applied Science and Convergence Technology
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• v.25 no.3
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• pp.56-60
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• 2016

The ALD process is an adequate technique to meet the requirements that come with the downscaling of semiconductor devices. To obtain thin films of the desired standard, it is essential to understand the thermal decomposition properties of the precursors. As such, this study examined the thermal decomposition properties of TEMAHf precursors and its effect on the formation of $HfO_2$ thin films. FT-IR experiments were performed before deposition in order to analyze the thermal decomposition properties of the precursors. The measurements were taken in the range of $135^{\circ}C-350^{\circ}C$. At temperatures higher than $300^{\circ}C$, there was a rapid decrease in the absorption peaks arising from vibration of $Sp^3$ C-H stretching. This showed that the precursors experienced rapid decomposition at around $275^{\circ}C-300^{\circ}C$. $HfO_2$ thin films were successfully deposited by Atomic Layer Deposition (ALD) at $50^{\circ}C$ intervals between $150^{\circ}C$ to $400^{\circ}C$; the deposited films were characterized using a reflectometer, X-ray photoelectron spectroscopy (XPS), Grazing Incidence X-ray Diffraction (GIXRD), and atomic force microscopy (AFM). The results illustrate the relationship between the thermal decomposition temperature of TEMAHf and properties of thin films.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.288-288
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• 2013

Lithium-ion battery (LIB) is one of the most important rechargeable battery and portable energy storage for the electric digital devices. In particular, study about the higher energy capacity and longer cycle life is intensively studied because of applications in mobile electronics and electric vehicles. Generally, the LIB's capacity can be improved by replacing anode materials with high capacitance. The graphite, common anode materials, has a good cyclability but shows limitations of capacity (~374 mAh/g). On the contrary, silicon (Si) and germanium(Ge), which is same group elements, are promising candidate for high-performance LIB electrodes because it has a higher theoretical specific capacity. (Si:4200 mAh/g, Ge:1600 mAh/g) However, it is well known that Si volume change by 400% upon full lithiation (lithium insertion into Si), which result in a mechanical pulverization and poor capacity retention during cycling. Therefore, variety of nanostructure group IV elements, including nanoparticles, nanowires, and hollow nanospheres, can be promising solution about the critical issues associated with the large volume change. However, the fundamental research about correlation between the composition and structure for LIB anode is not studied yet. Herein, we successfully synthesized various structure of nanowire such as Si-Ge, Ge-Carbon and Si-graphene core-shell types and analyzed the properties of LIB. Nanowires (NWs) were grown on stainless steel substrates using Au catalyst via VLS (Vapor Liquid Solid) mechanism. And, core-shell NWs were grown by VS (Vapor-Solid) process on the surface of NWs. In order to characterize it, we used FE-SEM, HR-TEM, and Raman spectroscopy. We measured battery property of various nanostructures for checking the capacity and cyclability by cell-tester.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.297.2-297.2
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• 2013

Scavenging electricity from wasteful energy resources is currently an important issue and piezoelectric nanogenerators (NGs) based on zinc oxide (ZnO) are promising energy harvesters that can be adapted to various portable, wearable, self-powered electronic devices. Although ZnO has several advantages for NGs, the piezoelectric semiconductor material ZnO generate an intrinsic piezoelectric potential of a few volts as a result of its mechanical deformation. As grown, ZnO is usually n-type, a property that was historically ascribed to native defects. Oxygen vacancies (Vo) that work as donors exist in ZnO thin film and usually screen some parts of the piezoelectric potential. Consequently, the ZnO NGs' piezoelectric power cannot reach to its theoretical value, and thus decreasing the effect from Vo is essential. In the present study, c-axis oriented insulator-like sputtered ZnO thin films were grown in various temperatures to fabricate an optimized nanogenerator (NGs). The purity and crystalinity of ZnO were investigated with photoluminescence (PL). Moreover, by introducing a p-type polymer usually used in organic solar cell, it was discussed how piezoelectric passivation effect works in ZnO thin films having different types of defects. Prepared ZnO thin films have both Zn vacancies (accepter like) and oxygen vacancies (donor like). It generates output voltage 20 time lager than n-type dominant semiconducting ZnO thin film without p-type polymer conjugating. The enhancement is due to the internal accepter like point defects, zinc vacancies (VZn). When the more VZn concentration increases, the more chances to prevent piezoelectric potential screening effects are occurred, consequently, the output voltage is enhanced. Moreover, by passivating remained effective oxygen vacancies by p-type polymers, we demonstrated further power enhancement.

• Korean Journal of Materials Research
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• v.16 no.10
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• pp.629-632
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• 2006

Electrical characteristics of Pt/Ti/Pt/Au and Pd/Zn/Pd/Au contacts to p-type InGaAs grown on an InP substrate have been characterized as a function of the doping concentration and the annealing temperature. The Pt/Ti/Pt/Au contacts produced the specific contact resistance as low as $2.3{\times}10^{-6}{\Omega}{\cdot}cm^2$, when heat-treated at an annealing temperature of $400^{\circ}C$. Comparison of the Pt/Ti/Pt/Au and Ti/Pt/Au contacts showed that the first Pt layer plays an important role in reducing the contact resistivity probably by lowering energy barrier at the metal-semiconductor interface. For the Pd/Zn/Pd/Au contacts, the contact resistivity remained virtually unchanged with increasing annealing temperature. The specific contact resistivity as low as $4.7{\times}10^{-6}{\Omega}{\cdot}cm^2$ was obtained. The results indicate that the Pt/Ti/Pt/Au and Pd/Zn/Pd/Au schemes could be potentially important for the fabrication of InP-based optoelectronic devices, such as photodetector and optical modulator.

• Korean Journal of Materials Research
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• v.22 no.10
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• pp.545-551
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• 2012

In semiconductor manufacturing, the circuit integrity of packaged BGA devices is tested by measuring electrical resistance using test sockets. Test sockets have been reported to often fail earlier than the expected life-time due to high contact resistance. This has been attributed to the formation of Sn oxide films on the Au coating layer of the probe pins loaded on the socket. Similar to contact failure, and known as "fretting", this process widely occurs between two conductive surfaces due to the continual rupture and accumulation of oxide films. However, the failure mechanism at the probe pin differs from fretting. In this study, the microstructural processes and formation mechanisms of Sn oxide films developed on the probe pin surface were investigated. Failure analysis was conducted mainly by FIB-FESEM observations, along with EDX, AES, and XRD analyses. Soft and fresh Sn was found to be transferred repeatedly from the solder bump to the Au surface of the probe pins; it was then instantly oxidized to SnO. The $SnO_2$ phase is a more stable natural oxide, but SnO has been proved to grow on Sn thin film at low temperature (< $150^{\circ}C$). Further oxidation to $SnO_2$ is thought to be limited to 30%. The SnO film grew layer by layer up to 571 nm after testing of 50,500 cycles (1 nm/100 cycle). This resulted in the increase of contact resistance and thus of signal delay between the probe pin and the solder bump.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.