• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.387-392
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• 2018

Static characteristics of SiC (silicon carbide) lateral p-i-n diodes implemented on semi-insulating substrate without an epitaxial layer are inVestigated. On-axis SiC HPSI (high purity semi-insulating) and VDSI (Vanadium doped semi-insulating) substrates are used to fabricate the lateral p-i-n diode. The space between anode and cathode ($L_{AC}$) is Varied from 5 to $20{\mu}m$ to inVestigate the effect of intrinsic-region length on static characteristics. Maximum breakdown Voltages of HPSI and VDSI are 1117 and 841 V at $L_{AC}=20{\mu}m$, respectiVely. Due to the doped Vanadium ions in VDSI substrate, diffusion length of carriers in the VDSI substrate is less than that of the HPSI substrate. A forward Voltage drop of the diode implemented on VDSI substrate is 12 V at the forward current of $1{\mu}A$, which is higher than 2.5 V of the diode implemented on HPSI substrate.

• 대한전자공학회논문지
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• 제12권4호
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• pp.35-40
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• 1975

ZnTe-lnSb Heterojunction을 계면합금법으로 제작했다. Insb의 In이 ZnTe결정에 확산되어 계면에 고저항 ZnTe충을 성장시켜 P-i-n구조를 갖고 있으며 전류수송기구는 p형 ZnTe 가전자대로부터 고저항 ZnTe충에 주입된 Hole의 SCLC기구에 의존된다. 순방향과 역방향 전압을 인가할때 실온에서 오런지색 전 장발장이 관측되었다. The Zn7e-lnSb heterojunctions was prepared by interface alloying technique. The structure of this beterojunction had p-i-n which semi-insulating ZnTe laver at interface of this heterojunction was formed by diffusing In of InSb into ZnTe crystal. The current transport mechanism of this heterojunction was Spacecharge-Limited-Current(SCLC) mechanism by hole at semi-insulating ZnTe layer. The hole wart injected from valence band of p- type SnTe crystal. Orange color electroluminescence was observed at this heterojunction when forward and reversed bias voltage applied.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.243-248
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• 2015

We prepared semi-insulating CdTe for radiation detectors by isothermal annealing of single crystals grown by Bridgeman technique in a sealed quartz container filled with Sn vapor. The resistivity of CdTe:Sn samples thus obtained was of order of $10^{10}Ohm{\cdot}cm$ at room temperature with electrons lifetime of $2{\times}10^{-8}$ s, which is appropriate for the applications desired. Analysis of electric transport characteristics depending on temperature, sample thickness and voltage applied revealed the presence of traps with concentration of about $(4-5){\times}10^{12}cm^{-3}$ with the corresponding energy level at 0.8 - 0.9 eV counted from the bottom of conduction band. The conductivity was determined by electron injection from electrodes in space charge limited current mode.

• E2M - 전기 전자와 첨단 소재
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• 제10권8호
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• pp.800-806
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• 1997

The behavior of de levels in rapid thermal annealed Fe-doped semi-insulating InP(100) was studied by photoinduced current transient spectrocopy(PICTS). In bulk InP, T2(Ec-0.24 eV), T3(Ec-0.30 eV) and T5(Ec-0.62 eV) traps were observed. After annealing the T2 trap was annihilated at 20$0^{\circ}C$ and recreated at 35$0^{\circ}C$. T3 trap was not affected below 40$0^{\circ}C$. With increasing temperature the concentration of T5 trap reduced and it was annihilated at 30$0^{\circ}C$. However the T1(Ec-0.16 eV) and T4(Ec-0.42 eV) traps were began to appear at 40$0^{\circ}C$and these concentrations were increased with annealing temperature. The T1 and T4 traps seem to be related to the isolated phosphorus vacancy( $V_{p}$) and $V_{p}$-indium antisite( $V_{p}$- $P_{in}$ ) or $V_{p}$-indium interstitial( $V_{p}$-I $n_{I}$) respectiely.respectiely.

• 한국통신학회논문지
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• 제25권9B호
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• pp.1635-1640
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• 2000

본 논문에서는 기본파를 억제시키고 2차 고조파가 주 발진신호로 동작되는 18GHz 대역의 push-push 발진기를 semi-MMIC 형태로 설계 및 제작하였다. 마이크로스트립 선로를 포함하는 passive component는 semi-insulating GaAs 기판위에 MMIC 공정을 이용하여 구현하고, Chip 형태의 P-HEMT, 저항, 캐패시터를 Au wire-bonding에의해 연결하였으며, via-hole 대신 접지면을 회로 주변에 구성하여, back-side와 wire-bonding하였다. 실험 결과 -10.5 dBm의 출력 전력 특성을 얻었으며, 기본 주파수 억압은 -17.3 dBc/Hz의 특성을 보였다. 위상 잡음은 100kHz offset에서 -97.7 dBc/Hz를 얻었다.

• 센서학회지
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• 제8권5호
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• pp.421-426
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• 1999

본 논문에서는 반절연성 GaAs(semi-insulating GaAs) 기판위에 $Al_2O_3$ 절연막이 게이트 절연막으로 이용된 공핍형모드 p-채널 GaAs MOSFET (depletion mode p-channel GaAs MOSFET)를 제조하였다. 반절연성 GaAs 기판위에 $1\;{\mu}m$의 GaAs 버퍼층(buffer layer), $4000\;{\AA}$의 p형 GaAs 에피층(epi-layer), $500\;{\AA}$의 AlAs층, 그리고 $50\;{\AA}$의 캡층(cap layer)을 차례로 성장시키고 습식열산화시켰으며, 이를 통하여 AlAs층은 완전히 $Al_2O_3$층으로 산화되었다. 제조된 MOSFET의 I-V, $g_m$, breakdown특성 측정을 통하여 AlAs/GaAs epilayer/S I GaAs 구조의 습식열산화는 공핍형 모드 p-채널 GaAs MOSFET를 구현하기에 적합함을 알 수 있다.

• 한국진공학회지
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• 제6권3호
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• pp.249-254
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• 1997

Fe가 첨가된 반절연성 InP(100)의 특성을 photoreflectance(R) 측정으로 조사하였다. 관측한 PR 신호로부터 300K에서 띠간격 에너지($E_o$)와 넓어지기 변수(broadening parameter:$\Gamma$)는 각각 1.336eV 및 11.2meV의 값을 얻었다. 측정온도를 300~80K로 낮춤에 따라 PR 신호는 엑시톤과 2차원의 띠사이 전이가 중첩된 형태(300K)에서 전형적인 엑시톤 에 의한 전이형태(80K)로 변함을 알았다. 또한 Varshni 계수 $\alpha=-0.94\pm$0.07meV/K, $\beta=587\pm$35.2K와 Bose-Einstein 계수 aB=33.6$\pm$2.02meV, $\theta=165\pm$33K의 값을 얻었다. 그리고 등온 및 등시 열처리를 수행한 후 측정 결과, 온도 $300^{\circ}C$에서 10~20분 정도 열처리시켰을 때 InP 시료의 결정성이 가장 좋아짐을 정성적으로 알 수 있었다.

• 한국광학회:학술대회논문집
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• 한국광학회 1991년도 제6회 파동 및 레이저 학술발표회 Prodeedings of 6th Conference on Waves and Lasers
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• pp.190-193
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• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

• 전자공학회논문지D
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• 제34D권7호
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• pp.56-61
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• 1997

I $n_{0.53}$G $a_{0.47}$As/I $n_{0.52}$A $l_{0.48}$As pseudomorphic high electron mobility transistor (P-HEMT) structures were grown on semi-insulating InP substrates by molecular beam epitzxy method. The hall effect measuremetn was used to measure the electrical properties and the photoluminescence (PL) measurement was used to measure the electrical properties and the photoluminescence(PL) measurement for optical propety. By the cross-sectional transmission electron microscopy (XTEM) investigation of the V and X shape defects including slip with angle of 60.deg. C and 120.deg. C to surface in the sampel, the defects formation mecahnism in the I $n_{0.52}$A $l_{0.48}$As epilayers on InP substrates could be explained with the different thermal expansion coefficients between I $n_{0.52}$A $l_{0.48}$As epilayers and InP substrate.d InP substrate.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.695-701
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• 2016

Be-doped GaSb layers were grown on highly mismatched semi-insulating GaAs substrate (001) with $2^{\circ}$ offcut towards <110> at low growth temperature, by molecular beam epitaxy (MBE). The influence of Be doping on the crystallographic quality, surface morphology, and electrical properties, was assessed by X-ray diffraction, Nomarski microscopy, and Hall effect measurements, respectively. Be impurities are well behaved acceptors with hole concentrations as high as $9{\times}10^{17}cm^{-3}$. In addition, the reduction of GaSb lattice parameter with Be doping was studied.