• Title/Summary/Keyword: Self-aligned

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Polymeric digital optical switch based on photobleached waveguides (광표백 폴리머 광도파로를 이용한 디지탈 광스위치)

  • 이상신;신상영
    • Korean Journal of Optics and Photonics
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    • v.7 no.4
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    • pp.414-418
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    • 1996
  • An electro-optic polymer digital optical switch was fabricated by using a photobleached waveguide and a self-aligned electrode. It features wavelength insensitive operation, fabrication tolerance and flexible design. And its possible advantages include low coupling losses to the fibers and wide bandwidths. For improving its switching performance, the guided mode profiles of the photobleached waveguides were controlled by photobleaching times to achieve optimized coupling in the branch. And the self-aligned electrode was employed to achieve both efficient overlap of the optical and electric fields and easy introduction of the adiabatically tapered electrodes. The measured crosstalks were better than -21dB at 1.32 ${\mu}{\textrm}{m}$ and 1.55 ${\mu}{\textrm}{m}$, and the extinction ratios of each output port were also more than 20 dB.

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A Study on the Channel Length and the Channel Punchthrough of Self-Aligned DMOS Transistor (자기정렬 DMOS 트랜지스터의 채널 길이와 채널 Punchthrough에 관한 고찰)

  • Kim, Jong-Oh;Kim, Jin-Hyoung;Choi, Jong-Su;Yoob, Han-Sub
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.11
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    • pp.1286-1293
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    • 1988
  • A general closed form expression for the channel length of the self-aligned double-diffused MOS transistor is obtained from the 2-dimensional Gaussian doping profile. The proposed model in this paper is composed of the doping concentration of the substrate, the final surface doping concentration and the vertical junction depth of the each double-diffused region. The calculated channel length is in good agreement with the experimental results. Also, the optimum channel structure for the prevention of the channel puncthrough is obtained by the averaged doping concentration in the channel region. A correspondence between the results of device simulation of channel punchthrough and the estimations of simplified model is confirmed.

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The fabrication process and optimum design of RESURF EDMOSFETs for smart power IC applications (Smart power IC용 RESURF EDMOSFETs의 제조공정과 최적설계)

  • 정훈호;권오경
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.7
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    • pp.176-184
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    • 1996
  • To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

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5-3: [Invited] Roll-to-Roll Manufacturing of Electronics on Flexible Substrates Using Self-Aligned Imprint Lithography (SAIL)

  • Kim, Han-Jun;Almanza-Workman, Marcia;Chaiken, Alison;Elder, Richard;Garcia, Bob;Jackson, Warren;Jeans, Albert;Kwon, Oh-Seung;Luo, Hao;Mei, Ping;Perlov, Craig;Taussig, Carl;Jeffrey, Frank;Beacom, Kelly;Braymen, Steve;Hauschildt, Jason;Larson, Don
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.82-85
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    • 2008
  • We are working towards large-area arrays of thin film transistors on polymer substrates using roll-to-roll (R2R) processes exclusively. Self-aligned imprint lithography (SAIL) is an enabler to pattern and align submicron features on meter-scaled flexible substrates in the R2R environment. The progress, current status and remaining issues of this new fabrication technology are presented.

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Nanoscale Floating-Gate Characteristics of Colloidal Au Nanoparticles Electrostatically Assembled on Si Nanowire Split-Gate Transistors

  • Jeon, Hyeong-Seok;Park, Bong-Hyun;Cho, Chi-Won;Lim, Chae-Hyun;Ju, Heong-Kyu;Kim, Hyun-Suk;Kim, Sang-Sig;Lee, Seung-Beck
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.2
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    • pp.101-105
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    • 2006
  • Nanoscale floating-gate characteristic of colloidal Au nanoparticles electrostatically assembled on the oxidized surface of Si nanowires have been investigated. The Si nanowire split-gate transistor structure was fabricated by electron beam lithography and subsequent reactive ion etching. Colloidal Au nanoparticles with ${\sim}5$ nm diameters were selectively deposited onto the Si nanowire surface by 2 min electrophoresis. It was found that electric fields applied to the self-aligned split side gates allowed charge to be transferred on the Au nanoparticles. It was observed that the depletion mode cutoff voltage, induced by the self-aligned side gates, was shifted by more than 1 V after Au nanoparticle electrophoresis. This may be due to the semi-one dimensional nature of the narrow Si nanowire transport channel, having much enhanced sensitivity to charges on the surface.

An Amorphous Silicon Local Interconnection (ASLI) CMOS with Self-Aligned Source/Drain and Its Electrical Characteristics

  • Yoon, Yong-Sun;Baek, Kyu-Ha;Park, Jong-Moon;Nam, Kee-Soo
    • ETRI Journal
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    • v.19 no.4
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    • pp.402-413
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    • 1997
  • A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

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Self-Aligned $n^+$ -pPolysilicon-Silicon Junction Structure Using the Recess Oxidation (Recess 산화를 이용한 자기정렬 $n^+$ -p 폴리실리콘-실리콘 접합구조)

  • 이종호;박영준;이종덕;허창수
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.6
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    • pp.38-48
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    • 1993
  • A recessed n-p Juction diode with the self-aligned sturcture is proposed and fabricated by using the polysilicon as an n$^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar divice and the n$^{+}$ polysilicone mitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition. As$^{+}$ dose for the doping of the polysilicon and the annealing condition using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS and the electrical characteristics are analyzed in terms of the ideality factor of diode (n), contact resistance and reverse leakage current. In addition, n$^{+}$-p junction diodes are formed by using the amorphous silicon (of combination of amorphous and polysiliocn) instead of polysilicon and their characteristics are compared with those of the standard sample. The As$^{+}$ dose for the formation of good junction is about 1~2${\times}10^{16}cm^{2}$ at given RTA conditions (1100.deg. C, 10sec).

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Design and Fabrication of Self-aligned Parallel-plate Type Micromirror Array (자기정렬에 의한 평판전극 마이크로미러 어린이의 설계와 제작)

  • Yoo, Byung-Wook;Kim, Min-Soo;Jin, Joo-Young;Jeon, Jin-A;Park, Jae-Hyong;Kim, Yong-Kweon
    • Proceedings of the KIEE Conference
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    • 2007.11a
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    • pp.150-151
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    • 2007
  • We present an one-axis parallel-plate type of bulk micromachined torsional micromirror array with single crystalline silicon (SCS) fabricated on the glass substrate. Structurally, bottom electrodes (amophous silicon) in this mirror are DRIEed along the aluminum mirror patterns on SCS, which are self-aligned with mirror plates. Tracing the history of the micromirror study, we found that few papers have been published on research for uniform driving voltages based upon the tilting direction. If there is a slight misalignment during anodic bonding between top (mirror plate) and bottom electrodes, the non-uniformity of driving voltage will be led depending on two different tilting direction. This paper discusses how much the pull-in voltages can be different due to misalignment between two electrodes. Moreover, We achieve uniform pull-in voltage regardless of misalignments in photolithography and anodic-bonding between two individual layers.

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Photoelectrochemical Properties of a Vertically Aligned Zinc Oxide Nanorod Photoelectrode (수직으로 정렬된 산화아연 나노막대 광전극의 광전기화학적 특성)

  • Park, Jong-Hyun;Kim, Hyojin
    • Journal of the Korean institute of surface engineering
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    • v.51 no.4
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    • pp.237-242
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    • 2018
  • We report on the fabrication and photoelectrochemical (PEC) properties of a ZnO nanorod array structure as an efficient photoelectrode for hydrogen production from sunlight-driven water splitting. Vertically aligned ZnO nanorods were grown on an indium-tin-oxide-coated glass substrate via seed-mediated hydrothermal synthesis method with the use of a ZnO nanoparticle seed layer, which was formed by thermally oxidizing a sputtered Zn metal thin film. The structural and morphological properties of the synthesized ZnO nanorods were examined using X-ray diffraction and scanning electron microscopy, as well as Raman scattering. The PEC properties of the fabricated ZnO nanorod photoelectrode were evaluated by photocurrent conversion efficiency measurements under white light illumination. From the observed PEC current density versus voltage (J-V) behavior, the vertically aligned ZnO nanorod photoelectrode was found to exhibit a negligible dark current and high photocurrent density, e.g., $0.65mA/cm^2$ at 0.8 V vs Ag/AgCl in a 1 mM $Na_2SO_4$ electrolyte. In particular, a significant PEC performance was observed even at an applied bias of 0 V vs Ag/AgCl, which made the device self-powered.

Polarization-Dependent Microlens Array Using Reactive Mesogen Aligned by Top-Down Nanogrooves for Switchable Three-Dimensional Applications

  • Son, Ki-Beom;Kim, Mugeon;Park, Min-Kyu;Kim, Hak-Rin
    • Journal of the Optical Society of Korea
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    • v.19 no.3
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    • pp.265-271
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    • 2015
  • We propose a reactive mesogen (RM) lens array to obtain good focusing behavior along with a short focal plane, where the focusing behavior is switchable according to the polarization state of incident light. Polarization-dependent focusing behavior is obtained using a planoconvex RM microlens array on a planoconcave isotropic lens template. Even though the sagitta of our RM lens is high, to obtain the short focal length, the RM layer can be aligned well by introducing a top-down alignment effect, using a nanogrooved template. The optical noise due to the $moir{\acute{e}}$ effect generated by the nanogrooves on the surface of the planoconvex RM layer can be removed simply by overcoating a thin RM layer, which is self-aligned by the geometric surface effect, without an additional alignment process. We demonstrate a hexagonal-packed RM lens array that has a very high fill factor and symmetric phase profile, for an ideal lens.