• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.2
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• pp.249-255
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• 1996

A self-aligned latch-up suppressed IGBT has been proposed and the process method and the device characteristics of the IGBT have been verified by numerical simulation. As the source is laterally diffused through the sidewall of the trench in the middle of the body, the size of the source is small and the doping concentration of the source is lower than that of the p++ body and the emitter efficiency of the parasitic npn transistor is low so that latch-up may be suppressed. No additional mask steps for p++ region, source, and source contact are required so that small sized body can be obtained Latch-u current density higher than 10000 A/cm$^{2}$ have been achieved by adjusting the process conditions.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.741-746
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• 1986

A novel n-p-n bipolar transistor of which emitter is self-aligned with base contact by polyilicon is developed for using in high speed and high packing density LSI circuits. The emitter of this transistor is separated less than 0.4 \ulcorner with base contact by self-aligh technology, and the emitter feature size is less than 3x5 \ulcorner\ulcorner Because the active region of this transistor is not damaged through all the process, it has excellent electric properties. Using the n-p-n transistors by 3.0\ulcorner design rules, a NTL ring oscillator has 380 ps, a CML ring oscillator has 390ps, and a I\ulcorner ring oscillator has 5.6ns of per-gate minimum propagation delay time.

• 한국전자현미경학회:학술대회논문집
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• 1997.05a
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• pp.80-82
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• 1997

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.56-57
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• 1998

• Transactions on Electrical and Electronic Materials
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• v.3 no.3
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• pp.8-13
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• 2002

Controlled precipitation of quasi-binary semiconductor system is newly proposed as an effective and reliable technique for the formation of well-defined and crystallographically aligned semiconductor nanostructures. Using HgTe-PbTe quasi-binary semiconductor system, self-aligned HgTe nanocrystallites distributed three dimensionally within PbTe matrix were successfully formed by the simple three step heat treatment process routinely found in age hardening process of metallic alloys. Examination of the resulting nano precipitates using conventional transmission electron microscopy (CTEM) and high resolution TEM (HRTEM) reveals that the coherent HgTe precipitates form as thin discs along the (100) habit planes making a crystallographic relation of {100}$\_$HgTe///{100}$\_$PbTe/ and [100]$\_$HgTe///[100]$\_$PbTe/. It is also found that the precipitate undergoes a gradual thickening and a faceting under isothermal aging up to 500 hours without any noticeable coarsening. These results, combined with the extreme dimension of the precipitates (4-5 nm in length and sub-nanometer in thickness) and the simplicity of the formation process, leads to the conclusion that controlled precipitation is an effective method for preparing desirable quantum-dot nanostructures.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.57-60
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• 2005

We have recently developed new organic TFT technologies such as self-aligned self-assembly (SALSA) process and a high-resolution color active-matrix LCD panel. A new method to realize high-resolution printable organic TFT array to drive active-matrix flat-panel display will be discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• Korean Journal of Optics and Photonics
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• v.7 no.3
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• pp.287-294
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• 1996

An optical phase modulator is fabricated in GaAs/AlGaAs doble heterostructure wafer grown by MOCVD. A self-aligned process, in which the same photoresist pattern is used for both the waveguide etching and the insulation layer formation, is developed and is found to be very useful, Fabry-Perot interference technique is applied to the measurement and the phase modulation efficiency is measured to be 22.5$^{\circ}$/Vmm at 1.31 ${\mu}{\textrm}{m}$ for TE polarization.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.773-776
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• 2007

A microstructure array has been proposed for micro plasma generation using electroplating and double exposed process. A stable atmospheric plasma has been generated at a low voltage by utilizing the micro electrode gap. Self-aligned microstructure can provide uniform electrode overlap with precisely controlled gap between the electrodes. The proposed structure allows for triode operation, which can expand the generated plasma over a large area by applying a lateral electric field. Electrical characteristics of the micro triode confirm the large numbers of the plasma ions are drifted to the secondary cathode by the lateral electrical field.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.461-464
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• 1998

Self-aligned AlGaAs/GaAs HBTs with the emitter area of 1.5*10.mu.$m^{2}$ were fabricated usng $WN_{x}$ as emitter metal. Their DC and RF characteristics were investigated. The common emitter current gain was 45 at $J_{c}$ = 6*$10^{4}$A/$cm^{2}$. From the Gummel plot, the ideality factors of $I_{c}$ and $I_{B}$ were 1.18 and 1.70, respectively. Emitter and base resistance were extracted from voltage drop region in gummel plot, and their values were 5.3.ohm. and 38.2.ohm.. The extrapolated $f_{T}$ = 72GHz and $f_{max}$ = 81GHz were obtained at $V_{CE}$ = 2V.