• 한국수자원학회:학술대회논문집
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• 한국수자원학회 2006년도 학술발표회 논문집
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• pp.546-551
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• 2006

It considered the population decrease and becoming older in age of the Rural area and operates by unmaned-non power which self-controlled gate developed. The operational principal used a buoyancy and when water level in the canal arrived to the set water level, in order for gate to be opened. The plate in order to fix to the shape in the canal which begs, it did in the quadrilateral and the rainfall it is sour intensively, canal bank comfort plate in order to ascend completely, it designed. The result which establishes Self-controlled gate, the gate upstream 1km until degree there was water level synergistic effect. It developed 4 as the research project and it established in Ah San city, and it establishes the Self-controlled gate of $B3.2m{\times}H2.4m$ size in Damyang and 100ha it does water supply in the rice field.

• 전자공학회논문지A
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• 제29A권2호
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• pp.77-79
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• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• 접착 및 계면
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• 제23권2호
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• pp.53-58
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• 2022

본 연구는 AlO_x유전체 표면에 유기 자립조립 단분자막 (self-assembled monolayer, SAM) 중간층을 도입함으로써 유전체의 표면특성을 제어하고, 최종적으로 유기전하변조트랜지스터 (Organic charge modulated field-effect transistor, OCMFET)의 전기적 특성을 향상시킨 결과를 제시하였다. 유기 중간층을 적용함으로써, OCMFET의 컨트롤 게이트(CG, Control gate)와 플로팅 게이트 (FG, Floating gate) 사이 커패시터 플레이트로 작용하는 산화알루미늄 게이트 유전체의 표면 에너지를 제어하였으며, FET의 가장 중요한 성능변수인 전계효과 이동도(field-effect transistor, μ_FET)를 향상시켰다. 사용된 SAMs은 네가지의 PA (Octadecylphosphonic acid, Butylphosphonic acid, (3-Bromopropyl)phosphonic acid, (3-Aminopropyl) phosphonic acid)를 사용하여 형성하였으며, 각각 0.73, 0.41, 0.34, 0.15 cm2V^-1s^-1의 μ_OCMFET를 나타내었다. 이 연구를 통해 유기 SAM 중간층의 알킬 체인(Alkyl chain)의 길이 및 말단기의 특성이 소자의 전기적 성능을 제어하는데 중요한 요인임을 확인하였으며, 이 결과를 통해 향후 최적의 센서 플랫폼으로서의 OCMFET 소자성능 최적화에 기여할 수 있을 것으로 기대한다.

• Journal of Power Electronics
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• 제17권4호
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• pp.1117-1126
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• 2017

The main contribution of this paper is the use of sensorless active diodes to generate the gate signals for a three-phase boost-rectifier with a self-powered control scheme. The sensorless operation is achieved making use of the gate control signals generated by the active diode schemes on each of the switching devices using a pulse width half-controlled boost rectifier modulation technique (PWM-HCBR). The proposed scheme synchronizes the gate control signals with a three phase voltage supply. Autonomous operation is obtained making use of the output DC bus to feed the control circuitry, the active diodes and the driver circuitry. The three-phase boost-rectifier is supplied by a three-phase permanent magnet electric generator powered by a solar concentrator dish with variable voltage and variable frequency conditions. Experimental results report an efficiency of up to 94.6% for 25 W and an input of 3.6 V peak per phase with 450.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.276-276
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• 2014

High-performance, fully-transparent, and top-gated oxide thin-film transistor (TFT) was successfully fabricated with Ta2O5 high-k gate dielectric on a glass substrate. Through a self-passivation with the gate dielectric and top electrode, the top-gated oxide TFT was not affected from H2O and O2 causing the electrical instability. Heat-treated InSnO (ITO) was used as the top and source/drain electrode with a low resistance and a transparent property in visible region. A InGaZnO (IGZO) thin-film was used as a active channel with a broad optical bandgap of 3.72 eV and transparent property. In addition, using a X-ray diffraction, amorphous phase of IGZO thin-film was observed until it was heat-treated at 500 oC. The fabricated device was demonstrated that an applied electric field efficiently controlled electron transfer in the IGZO active channel using the Ta2O5 gate dielectric. With the transparent ITO electrodes and IGZO active channel, the fabricated oxide TFT on a glass substrate showed optical transparency and high carrier mobility. These results expected that the top-gated oxide TFT with the high-k gate dielectric accelerates the realization of presence of fully-transparent electronics.

• 전자공학회논문지
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• 제53권9호
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• pp.54-61
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• 2016

본 논문에서는 6 Gbps 고속 double data rate(DDR) 인터페이스를 위한 기준 전압 발생기와 선형 등화기를 포함하는 단일 종단 수신기를 제안한다. 제안하는 단일 종단 수신기는 낮은 전압 레벨의 입력 신호에 대해 전압 이득을 증가시키기 위해 공통 게이트 증폭기를 사용한다. 저주파의 이득을 줄이고 고주파 피킹 이득을 발생시키는 연속 시간 선형 등화기가 공통 게이트 증폭기에서의 구현을 위해 제안된다. 또한, 공통 게이트 증폭기의 오프셋 노이즈를 줄임으로 전압이득을 극대화하기 위해 기준 전압 발생기가 구현된다. 제안하는 기준 전압 발생기는 디지털 평준화 기법에 의해 2.1 mV의 해상도로 제어된다. 제안된 단일 종단 수신기는 공급전압 1.2 V의 65 nm CMOS 공정에서 설계되었으며 6 Gbps의 동작속도에서 15 mW의 전력을 소모한다. 설계된 등화기는 저주파에서의 이득 대비 3 GHz 주파수에서의 피킹 이득을 5 dB 이상 증가시킨다.

• 전자공학회논문지SC
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• 제39권2호
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• pp.140-145
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• 2002

본 논문은 단락회로 전류를 없애기 위한 CMOS 버퍼회로에 대한 것이다. 최종 구동소자는 풀-업 PMOS와 풀-다운 NMOS로 구성하고 이를 구동하기 위해 두가지 경로를 입력신호로 선택되도록 하였다. 이러한 기법으로 최종 구동회로가 짧은 시간동안 tri-state가 되어 단락회로 전류를 차단하였다. 모의 실험결과 전원전압 3.3V에서 전력-지연 곱을 기존의 Tapered 버퍼[1]와 비교하여 약 42% 줄일 수 있었다

• 한국진공학회지
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• 제7권2호
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• pp.88-93
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• 1998

본 연구에서는 기계-화학적 연마(Chemical-Mechanical-Polishing: CMP)공정을 이용 하여 게이트 전극을 가지는 실리콘 전계방출 소자를 제작하였으며, 또한 그 전자방출 특성 을 분석하였다. 실리콘 전계방출 소자를 제작하기 위해 실리콘을 두단계로 이루어진 건식식 각과 산화공정으로 팁을 뾰족하게 만들었으며, 게이트를 형성하기 위하여 고 선택비를 가지 는 CMP공정을 사용하였으며, 연마 시간과 연마 압력의 변화로 게이트 높이와 개구의 직경 을 쉽게 조절할 수 있었다. 또한, CMP공정시 발생되는 디싱(dishing)문제를 산화막 마스킹 을 사용함으로 해결하여 자동 정렬된 게이트전극의 개구를 깨끗하게 형성할 수 있었다. 제 작된 에미터의 높이와 팁끝의 반경은 각각 1.1$\mu$m, 100$\AA$정도이며, 제작된 2809개의 팁 어 레이로 80V의 게이트전압에서 31$\mu$A의 방출전류를 얻을 수 있었다.

• Journal of Power Electronics
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• 제5권2호
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• pp.109-119
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• 2005

This paper deals with the performance analysis of static compensator (STATCOM) based voltage regulator for self­excited induction generators (SEIGs) supplying balanced/unbalanced and linear/ non-linear loads. In practice, most of the loads are linear. But the presence of non-linear loads in some applications injects harmonics into the generating system. Because an SEIG is a weak isolated system, these harmonics have a great effect on its performance. Additionally, SEIG's offer poor voltage regulation and require an adjustable reactive power source to maintain a constant terminal voltage under a varying load. A three-phase insulated gate bipolar transistor (IGBT) based current controlled voltage source inverter (CC- VSI) known as STATCOM is used for harmonic elimination. It also provides the required reactive power an SEIG needs to maintain a constant terminal voltage under varying loads. A dynamic model of an SEIG-STATCOM system with the ability to simulate varying loads has been developed using a stationary d-q axes reference frame. This enables us to predict the behavior of the system under transient conditions. The simulated results show that by using a STATCOM based voltage regulator the SEIG terminal voltage can be maintained constant and free from harmonics under linear/non linear and balanced/unbalanced loads.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.202-207
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• 1997

Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.