• Title/Summary/Keyword: Selective Transistor

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Fabrication of An Organic Thin-Film Transistor Array by Wettability Patterning for Liquid Crystal Displays

  • Kim, Sung-Jin;Bae, Jin-Hyuk;Ahn, Taek;Suh, Min-Chul;Chang, Seung-Wook;Mo, Yeon-Gon;Chung, Ho-Kyoon;Lee, Sin-Doo
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.151-154
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    • 2007
  • We demonstrate a novel selective patterning process of a semiconducting polymer for channel regions to fabricate an array of organic thin-film transistors (OTFTs). This process is applicable for various organic films over large area. A reflective liquid crystal display based on the OTFT array was produced using the selective patterning through a wettability control.

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Generalized Selective Harmonic Elimination Modulation for Transistor-Clamped H-Bridge Multilevel Inverter

  • Halim, Wahidah Abd.;Rahim, Nasrudin Abd.;Azri, Maaspaliza
    • Journal of Power Electronics
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    • v.15 no.4
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    • pp.964-973
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    • 2015
  • This paper presents a simple approach for the selective harmonic elimination (SHE) of multilevel inverter based on the transistor-clamped H-bridge (TCHB) family. The SHE modulation is derived from the sinusoidal voltage-angle equal criteria corresponding to the optimized switching angles. The switching angles are computed offline by solving transcendental non-linear equations characterizing the harmonic contents using the Newton-Raphson method to produce an optimum stepped output. Simulation and experimental tests are conducted for verification of the analytical solutions. An Altera DE2 field-programmable gate array (FPGA) board is used as the digital controller device in order to verify the proposed SHE modulation in real-time applications. An analysis of the voltage total harmonic distortion (THD) has been obtained for multiple output voltage cases. In terms of the THD, the results showed that the higher the number of output levels, the lower the THD due to an increase number of harmonic orders being eliminated.

Realization of 1D-2DEG Composite Nanowire FET by Selective Area Molecular Beam Epitaxy (선택적 분자선 에픽택시 방법에 의한 1D-2DEG 혼성 나노선 FET의 구현)

  • Kim, Yun-Joo;Kim, Dong-Ho;Kim, Eun-Hong;Seo, Yoo-Jung;Roh, Cheong-Hyun;Hahn, Cheol-Koo;Ogura, Mutsuo;Kim, Tae-Geun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.11
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    • pp.1005-1009
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    • 2006
  • High quality three-dimensional (3D) heterostructures were constructed by selective area (SA) molecular beam epitaxy (MBE) using a specially patterned GaAs (001) substrate to improve the efficiency of tarrier transport. MBE growth parameters such as substrate temperature, V/III ratio, growth ratio, group V sources (As2, As4) were varied to calibrate the selective area growth conditions and the 3D GaAs-AlGaAs heterostructures were fabricated into the ridge type and the V-groove type. Scanning micro-photoluminescence $({\mu}-PL)$ measurements and the following analysis revealed that the gradually (adiabatically) coupled 1D-2DEG (electron gas) field effect transistor (FET) system was successfully realized. These 3D-heterostructures are expected to be useful for the realization of high-performance mesoscopic electronic devices and circuits since it makes it possible to form direct ohmic contact onto the (quasi) 1D electron channel.

Realization of 1D-2DEG Composite Nanowire FET by Selective Area Molecular Beam Epitaxy (선택적 분자선 에피택시 방법에 의한 1D-2DEG 혼성 나노선 FET의 구현)

  • Kim, Yun-Joo;Kim, Eun-Hong;Seo, Yoo-Jung;Kim, Dong-Ho;Hahn, Cheol-Koo;Ogura, Mutsuo;Kim, Tae-Geun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.167-168
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    • 2006
  • High quality 3D-heterostructures were constructed by selective area (SA) molecular beam epitaxy (MBE) using a specially patterned GaAs (001) substrate. MBE growth parameters such as substrate temperature, V/III ratio, growth ratio, group V sources ($As_2$, $As_4$) were varied to calibrate the selective area growth conditions. Scanning micro-photoluminescence ($\mu$-PL) measurements and following analysis revealed that the gradually (adiabatically) coupled 2DEG-1D-1DEG field effect transistor (FET) system was realized. This 3D-heterostructure is very promising for the realization of the meso-scopic electronic devices and circuits since it makes it possible to form direct ohmic contact to the (quasi) 1DEG.

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A Study on Poly-Si TFT characteristics with string structure for 3D SONOS NAND Flash Memory Cell (3차원 SONOS 낸드 플래쉬 메모리 셀 적용을 위한 String 형태의 폴리실리콘 박막형 트랜지스터의 특성 연구)

  • Choi, Chae-Hyoung;Choi, Deuk-Sung;Jeong, Seung-Hyun
    • Journal of the Microelectronics and Packaging Society
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    • v.24 no.3
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    • pp.7-11
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    • 2017
  • In this paper, we have studied the characteristics of NAND Flash memory in SONOS Poly-Si Thin Film Transistor (Poly-Si TFT) device. Source/drain junctions(S/D) of cells were not implanted and selective transistors were located in the end of cells. We found the optimum conditions of process by means of the estimation for the doping concentration of channel and source/drain of selective transistor. As the doping concentration was increased, the channel current was increased and the characteristic of erase was improved. It was believed that the improvement of erase characteristic was probably due to the higher channel potential induced by GIDL current at the abrupt junction. In the condition of process optimum, program windows of threshold voltages were about 2.5V after writing and erasing. In addition, it was obtained that the swing value of poly Si TFT and the reliability by bake were enhanced by increasing process temperature of tunnel oxide.

Complementary FET-The Future of the Semiconductor Transistor (Complementary FET로 열어가는 반도체 미래 기술)

  • S.H. Kim;S.H. Lee;W.J. Lee;J.W. Park;D.W. Suh
    • Electronics and Telecommunications Trends
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    • v.38 no.6
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    • pp.52-61
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    • 2023
  • With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

Laser Sintering of Silver Nanoparticle for Flexible Electronics (유연소자 응용을 위한 은 나노입자의 레이저 소결)

  • Jia, Seok Young;Park, Won Tea;Noh, Yong-Young;Chang, Won Seok
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.24 no.1
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    • pp.135-139
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    • 2015
  • We present a fine patterning method of conductive lines on polyimide (PI) and glass substrates using silver (Ag) nanoparticles based on laser scanning. Controlled laser irradiation can realize selective sintering of conductive ink without damaging the substrate. Thus, this technique easily creates fine patterns on heat-sensitive substrates such as flexible plastics. The selective laser sintering of Ag nanoparticles was managed by optimizing the conditions for the laser scan velocity (1.0-20 mm/s) and power (10-150 mW) in order to achieve a small gap size, high electrical conductivity, and fine roughness. The fabricated electrodes had a minimum channel length of $5{\mu}m$ and conductivity of $4.2{\times}10^5S/cm$ (bulk Ag has a conductivity of $6.3{\times}10^5S/cm$) on the PI substrate. This method was used to successfully fabricate an organic field effect transistor with a poly(3-hexylthiophene) channel.

Development of Selective GaN etching Process for p-GaN/AlGaN/GaN E-mode FET Fabrication (p-GaN/AlGaN/GaN E-mode FET 제작을 위한 선택적 GaN 식각 공정 개발)

  • Jang, Won-Ho;Cha, Ho-Young
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.24 no.2
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    • pp.321-324
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    • 2020
  • In this work, we developed a selective etching process for GaN that is a key process in p-GaN/AlGaN/GaN enhancement-mode (E-mode) power switching field-effect transistor (FET) fabrication. In order to achieve a high current density of p-GaN/AlGaN/GaN E-mode FET, the p-GaN layer beside the gate region must be selectively etched whereas the underneath AlGaN layer should be maintained. A selective etching process was implemented by oxidizing the surface of the AlGaN layer and the GaN layer by adding O2 gas to Cl2/N2 gas which is generally used for GaN etching. A selective etching process was optimized using Cl2/N2/O2 gas mixture and a high selectivity of 53:1 (= GaN/AlGaN) was achieved.

Photocurrent of CdSe nanocrystals on singlewalled carbon nanotube-field effect transistor

  • Jeong, Seung-Yol;Lim, Seung-Chu;Lee, Young-Hee
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.03b
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    • pp.40-40
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    • 2010
  • CdSe nanocrystals (NCs) have been decorated on singlewalled carbon nanotubes (SWCNTs) by combining a method of chemically modified substrate along with gate-bias control. CdSe/ZnS core/shell quantum dots were negatively charged by adding mercaptoacetic acid (MAA). The silicon oxide substrate was decorated by octadecyltrichlorosilane (OTS) and converted to hydrophobic surface. The negatively charged CdSe NCs were adsorbed on the SWCNT surface by applying the negative gate bias. The selective adsorption of CdSe quantum dots on SWCNTs was confirmed by confocal laser scanning microscope. The measured photocurrent clearly demonstrates that CdSe NCs decorated SWCNT can be used for photodetector and solar cell that are operable over a wide range of wavelengths.

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