• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1068-1070
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• 2005

This study sorted high voltage motors by the voltage and the capacity and analyzed the property of motor-start. So we found out some problems of the starting circuit from several sites, and made the answers of the problems. If these results of our study are utilized in new WTPs, the safety of the starting circuit will be improved and the life of electric power system will be longer. We recommend this study as a reference when our company founds the standard of electric facility design.

• Journal of information and communication convergence engineering
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• v.18 no.4
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• pp.245-253
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• 2020

The human body and nervous system transmit information through electric charges. After the electric charge transmits information to the brain, we can feel pain, numbness, comfort, and other feelings. Electric therapy is currently used widely in clinical practice because the field of examination is more representative of electrocardiogram, and in the field of treatment is more representative of electrotherapy. In this study, we design a system for neurophysiological therapy and conduct parameter calculation and model selection for the components of the system. The system is based on a discontinuous conduction mode (DCM) boost circuit, and controlled and regulated by a single-chip microcomputer. The system does not only have a low cost but also fully considers the safety of use, convenience of the human-computer interface, adjustment sensitivity, and waveform diversity in the design. In future, it will have strong implications in the field of electrotherapy.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.12
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• pp.2311-2317
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• 2011

In this paper, we study the temperature change of a ${\mu}$-bolometer focal plane array with a capacitive transimpedance amplifier bias cancellation circuit. Thermal analysis is essential to understand the performance of a ${\mu}$-bolometer focal plane array, and to improve the temperature stability of a focal plane array characteristics. In this study, the thermal analyses of a ${\mu}$-bolometer and its two reference detectors are carried out as a function of time. The analyses are done with the $30{\mu}m$ pitch $320{\times}240$ focal plane array operating of 60 Hz frame rate and having a columnwise readout. From the results, the temperature increase of a ${\mu}$-bolometer in FPA by an incident IR is estimated as $0.689^{\circ}C$, while the temperature increase by a pulsed bias as $7.1^{\circ}C$, which is about 10 times larger than by IR. The temperature increase of a reference detector by a train of bias pulses may be increased much higher than that of an active ${\mu}$-bolometer. The suppression of temperature increase in a reference bolometer can be done by increasing the thermal conductivity of the reference bolometer, in which the selection of thermal conductivity also determines the range of CTIA output voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.69-76
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• 2007

A new circuit design for Bus-Invert Coding is presented in this paper. The new scheme sends the coding information through the bus-lines instead of the invert-line which has been used conventionally for many types of Bus-Invert algorithms. By employing a newly developed bus-driver called Flip-Driver and a selection circuit, it not only removes the invert-line but suppresses the additional bus-transitions in sending coding information. It is verified by simulations that the efficiency of various Bus-Invert algorithms is increased about 40% to 100% by employing the new design.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.9
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• pp.59-64
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• 2015

IEC is an international standards which are used in many countries with Europe as the center. IEC standard is introduced in Korea according to WTO/TBT agreements, however until now there are no buildings in Korea which are designed applying IEC standard. Therefore, KEA(Korea Electric Association) is scheduled to construct Korean low voltage electrical installation integration test site which is designed applying IEC standard. In this paper, before being under construction of Korean low voltage electrical installation integration test site, power substation is modeled based on real design parameters and method to select circuit breakers and cables is presented applying IEC standard in the modeled power substation. EMTP(ElctroMagnetic Transient Program) is used for simulation program. EMTP which is power system analysis program is easy to model power system and power substation.

• Transactions of the Korean hydrogen and new energy society
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• v.26 no.3
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• pp.278-286
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• 2015

This paper presents the analytical results of the thermodynamic performance characteristics for a cogeneration system using regenerative organic Rankine cycle (ORC) driven by low-grade heat source. The combined heat and power cogeneration system consists of a regenerative superheated ORC and an additional process heater in a series circuit. Eight working fluids of R134a, R152a, propane, isobutane, butane, R245fa, R123, and isopentane are considered for the analysis. Special attention is paid to the effect of turbine inlet pressure on the system performance such as thermal input, net power and useful heat productions, electrical, thermal, and system efficiencies. The results show a significant effect of the turbine inlet pressure and selection of working fluid on the thermodynamic performance of the system.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.143-148
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• 1998

The Design criteria of the auxiliary resonant snubber inverter (ARSI) using a load-side circuit are discussed in relation to electric propulsion drives. In this regard, this paper attempts to develop a set of design criteria for the ARSI. First, the switching characteristics of IGBTs under soft-switching mainly in terms of dv/dt/, di/dt and switching losses are discussed and utilized for optimizing the selection of the resonant components in the system. After that, the proper control strategies of ARSIs are analyzed and simulated based on voltage space vector modulations. Later, the design, control and implementation of the auxiliary resonant circuit suitable for industrial products are analyzed and presented. And finally, other factors including power stage layout, packaging and the choice of current sensors are included. The detailed simulation and experimental results will be included based on a laboratory prototype. The proposed design criteria of the ARSI would help the implementation of an electric propulsion drive system.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.97-102
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• 2001

In computer-aided design, partitioning is task of clustering objects into groups to that a given objection function is optimized It is used at the layout level to fin strongly connected components that can be placed together in order to minimize the layout area and propagation delay. Partitioning can also be used to cluster variables and operation into groups for scheduling and unit selection in high-level synthesis. The most popular algorithms partitioning include the Kernighan-Lin algorithm Fiduccia-Mattheyses heuristic and simulated annealing In this paper we propose a genetic algorithm searching solution space for the circuit partitioning problem. and then compare it with simulated annealing by analyzing the results of implementation.

• ETRI Journal
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• v.33 no.5
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• pp.752-758
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• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.