• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.95-102
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• 2015

This paper proposes a simple algorithm for circuit minimization. There are currently two effective heuristics for circuit minimization, namely manual Karnaugh maps and computable Quine-McCluskey algorithm. The latter, however, has a major defect: the runtime and memory required grow $3^n/n$ times for every increase in the number of variables n. The proposed algorithm, however, extracts the prime implicants (PI) that cover minterms of a given Boolean function by deriving an implicants table based on frequency. From a set of the extracted prime implicants, the algorithm then eliminates redundant PIs again based on frequency. The proposed algorithm is therefore capable of minimizing circuits polynomial time when faced with an increase in n. When applied to various 3-variable and 4-variable cases, it has proved to swiftly and accurately obtain the optimal solutions.

• Journal of the Korean Society for Railway
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• v.19 no.4
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• pp.468-479
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• 2016

In order to supply power to online monitoring systems that are attached to high voltage catenary or overhead wires, a wireless power transfer system is required that is able to transmit power over the insulation gap. Such wireless power transfer systems have transmitter and receiver coils that have diameters of over 10cm. This paper focused on an investigation of the sources of loss in the coils when the coils are fabricated using printed circuit board technology. Using finite element simulation results, it has been shown that the dielectric loss in the substrate was the dominant source of the total loss. It has been demonstrated that the selection of a proper dielectric material was the most critical factor in reducing the loss. For further reduction of the loss, the distributed tuning capacitor method and the slotting of the inter-turn spaces have been proposed. For the evaluation of the proposed methods, four coils have been fabricated and their equivalent series resistances and quality factors were measured. Measured quality factors were greater than 300, which means that these devices will be helpful in achieving high coil-to-coil efficiency.

• Journal of the Korea Society of Computer and Information
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• v.25 no.12
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• pp.349-357
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• 2020

In this paper, I propose a presentation examples of the development of teaching materials using Arduino. For this purpose, a six-step low-cost microcontroller teaching-learning development model was used, the steps being topic selection, exploration of implementation methods, experimentation, production of teaching and learning materials, implementing lesson plans, and improvement. After analyzing the composition of the source code and circuits introduced in the existing Arduino book, this content was reconstructed to fit the programming education context. A simple method of constructing a circuit using materials such as Arduino and a piezo buzzer is proposed to save time on circuit composition. Using this circuit, examples of use in teaching-learning activities for various programming content elements are presented. The core concept of this study is that it provides a direct experience of the content of C language programming exercises that can only be found on existing screens.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2395-2402
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• 2013

An active-RC channel selection filter (CSF) with the bandwidth of 40MHz and the improved linearity is proposed in this paper. The proposed CSF is the fifth butterworth filter which consists of a first order low pass filter, two second order low pass filters of a biquad architecture, and DC feedback circuit for cancellation of DC offset. To improve the linearity of the CSF, a body node of a MOSFET for a switch is connected to its source node. The bandwidth of the designed CSF is selected to be 10MHz, 20MHz and 40MHz and its voltage gain is controlled by 6 dB from 0 dB to 24 dB. The proposed CSF is designed by using 40nm 1-poly 8-metal CMOS process with a 1.2V. When the designed CSF operates at the bandwidth of 40 MHz and voltage gain of 0 dB, the simulation results of OIP3, in-band ripple, and IRN are 31.33dBm, 1.046dB, and 39.81nV/sqrt(Hz), respectively. The power consumption and layout area are $450{\times}210{\mu}m^2$ and 6.71mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.67-79
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• 1996

This paper presents a composite luminance signal processing system for NTSC, PAL and SECAM standards. Eaxh of the three standards employs its own specifications of subcarmier bandwidth and luminance signal waveform. The proposed system, compatible to the specifications of the three standard and B/W TV, implements variable freqneucy characteristics by controlling filter coefficients. The major features of the system are a luminance/chroma separation unit and an aperture compensation unit. The luminance/chroma separation unit employes a notch filter selection a trap freqneyc to atenuate unwanted color signals in luminance signal bands. The aperture compensation unit comprises two subunits, to provide clear color definition for each of the three standards: a primary compensation circuit and a variable compensation circuits. The proposed system yields a 40 dB gain from the chroma/luminance separation and a 10 dB gain from the aperture compensation unit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1259-1265
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• 2006

In this paper, we propose a combined synthetic algorithm of the logic level for high speed FPGA design. The algorithm divides critical path to reduce delay time and generates a circuit which the divided circuits execute simultaneously. This kernel selection algorithm is made by C-langage of SUN UNIX. We compare this with the existing FlowMap algorithm. This proposed algorithm shows result on 33.3% reduction of delay time by comparison with the existing algorithm.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.891-895
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• 2004

This paper suggests the techniques in determining the values of the steady-state equivalent circuit parameters of a three-phase squirrel-cage induction machine using immune algorithm. The parameter estimation procedure is based on the steady state phase current versus slip and input power versus slip characteristics. The proposed estimation algorithm is of a nonlinear kind based on clonal selection in immune algorithm. The machine parameters are obtained as the solution of a minimization of least-squares cost function by immune algorithm. Simulation shows better results than the conventional approaches.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.7-10
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• 2004

This paper describes techniques to implement low-cost adapt ive Pipelined LMS filter for ASIC implement ions of high communication receivers. Power consumpiton can be reduced using a careful selection of architectural, algorithmic, and VLSI circuit techlifue A Pipelined architecture for the strength-reduced algorithm is then developed via the relaxed look-ahead transformation. This technique, which is an approximation of the conventional look-ahead compution, maintains the functionality of the algorithm rather than the input-output behavior Convergence maiysis of the Proposed architecture has been presented and support via simulation results. The resulting pipelined adaptive filter achives a higher though put requires lower power as compared to the filter using the serial algorithm.

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.54-60
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• 1994

In this paper, the multi-sensor signal processing IC is designed. It consists of an analog multiplexer for selection of multi-sensor signals, active filters for noise rejection and signal amplification, and a sample and hold circuit for interface with digital signal processing. By implementing these circuits with CMOS transistors, integration, low power dissipation and miniaturization of the total signal processing system have been made possible.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.505-507
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• 2004

This paper attempts to compensate the nonlinearity between the input voltage and the output displacement of the piezoelectric stack in dynamic actuation by the following two ways. Firstly, the charge steering by circuit configuration reduces the hysteresis of piezoelectric actuator remarkably. However, it makes the ripple in positioning due to the phase lag and noise induced from the elements of the long closed loop. Secondly, the feedforward control by neural network compensates the hysteresis of the piezoelectric actuators effectively with the appropriate selection of the input variables for the training. The improvement of the dynamic performance of the piezoelectric actuators by the developed linearization technique is verified by experiments.