• The Korean Journal of Ceramics
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• v.2 no.2
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• pp.95-101
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• 1996

Variations of the leakage current behaviors and interface potential barrier $({\Phi}_B)$ of rf-sputter deposited (Ba, Sr)$TiO_3$ (BST) thin films with thicknesses ranging from 20 nm to 150nm are investigated as a function of the thickness and bias voltages. The top and bottom electrodes are dc-sputter-deposited Pt films. ${\Phi}_B$ critically depends on the BST film deposition temperature, postannealing atmosphere and time after the annealing. The postannealing under $N_2$ atmosphere results in a high interface potential barrier height and low leakage current. Maintaining the BST capacitor in air for a long time reduces the ${\Phi}_B$ from about 2.4 eV to 1.6 eV due to the oxidation. ${\Phi}_B$ is not so dependent on the film thickness in this experimental range. The leakage conduction mechanism is very dependent on the BST film thickness; the 20 nm thick film shows tunneling current, 30 and 40 nm thick films show Shottky emission current.

• Journal of Industrial Technology
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• v.28 no.A
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• pp.177-184
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• 2008

A low loss frequency doubler operated on low power for the RFID harmonic tags is presented. Using the excellent nonlinear characteristics of the Schottky barrier diode and proper matching networks between the diode and ports, the low conversion loss of the harmonic tag is accomplished. This doubler could be used to increase the detectable distance of the conventional RFID system adopted harmonic tags.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.75.2-75.2
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• 2009

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.431-434
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• 2008

The physical OLED analog behavioral model for SPICE simulation has been described using Verilog-A language. The model is based on the carrier-balance between the hole and electron injected through Schottky barrier at anode and cathode. The accuracy of this model was examined by comparing with the results from device simulation.

• Journal of Information Display
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• v.10 no.3
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• pp.101-106
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• 2009

In this study, a physical OLED analog behavior model for SPICE simulation was described using the Verilog-A language. The model was presented through theoretical equations for the J-V characteristics of OLED derived according to the internalcarrier emission equation based on a diffusion model at the Schottky barrier contact, and the mobility equation based on the Pool-Frenkel model. The accuracy of this model was examined by comparing it with the results of the device simulation that was conducted.

• Proceedings of the Korean Ceranic Society Conference
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• 2003.04a
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• pp.40.2-40
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• 2003

• Proceedings of the KIEE Conference
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• 2003.07e
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• pp.24-27
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• 2003

In this paper, We make experiment on two methode for GaAs MESFET with temperature variation. One method, we mesure gate leakage current at open source electrode. another we mesure gate leakage current at short source electrode. The difference of two current has been tested and provide that the existence of another source to Schottky barrier height against the image force lowering effect.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.9
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• pp.349-354
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• 1985

The conducting currents of polypropylene film was measured a function with electric fields at temperature of 25,35,45( C). It appears that there are four regions of conducting currents, depending upon the strength of the applied electric field` ohmic region based on ionic conduction, Poole-Frenkel region, Schottky region and negative resistance region. Several information of dielectric constant and potential barrier height were obtained.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1212-1215
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• 2009

The theoretical equations for J-V characteristics in an OLED was derived according to the internal carrier emission equation based on a diffusion model at Schottky barrier contact and the mobility equation based on the Pool-Frenkel model. The J-V characteristics of OLED are presented using a behavioral model for analog systems (Verilog-A language), and the accuracy of this model was verified by comparing with the device simulation results.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.206-210
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• 1986

Double Ion Implantation methods are used to improve the stiffness os carrier profiles, and then the analytical solutions to Poisson`s equation are derived with summation of each carrier profile. Numerical analyses are done using profer boudary conditions and the results show that the improvement of voltage-dependent-capacitance ratio (C(!)/C(25)) is obtained up to B.6. The third ion implantation is for the enhancement of the Schottky barrier height.