• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.5 s.335
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• pp.13-22
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• 2005

IEEE 802.11a is a standard for the high-speed wireless local area network (WLAN), supporting from 6 up to 54 Mbps in a 5 GHz band. We propose a channel equalization algerian and a sampling clock recovery algorithm by utilizing the Viterbi decoder output of the IEEE 802.11a WLAN standard. The proposed channel equalizer adaptively compensates channel variations. The proposed system uses re-encoded Viterbi decoder outputs as reference symbols for the adaptation of the channel equalizer. It also extracts sampling phase information with the Viterbi decoder outputs for fine adjustment of the sampling clock. The proposed sampling clock recovery and equalizer are more robust to noise and frequency selective fading environments than conventional systems using only four pilot samples.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1695-1699
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• 2012

This paper is proposed all digital wide-range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per $2{\pi}$/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13um CMOS process and verified simulation to spectre tool.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.95-99
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• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.12
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• pp.31-39
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• 1993

In the playback signal processing of a digital magnetic recording system, the major signal processing processes consist of pulse equalization. pulse detection, clock recovery, and data recovery. Equalizer which compensates interference occurrde between pulses recorded in high density on a magnetic media is realized by pulse slimming method, and pulse detection by a integrating detector. Clock recovery from the detector output was accomplished by using PLL. and data recovery to reduce noise effects was carried out by utilizing the three sampling clocks recovered in clock recovery process. In this paper these processes are implemented in hardware and its performance is evaluated by experimenting with a commercial DAT. It was found that the playback signal processor proposed is suitable to the practical high density magnetic recording system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.7
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• pp.545-551
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• 2013

Timing recovery loop composed of the Timing Error Detector(TED), loop filter and resampler is widely used for the timing synchronization in MQASK receivers. Since TED is sensitive to the delay between the symbol period of the signal and sampling period, the output is averaged out when the symbol rate and sampling rate are quite different the recovery loop cannot work at all. This paper presents a sampling frequency discriminator (SRD), which detects the frequency offset of the sampling clock to the symbol clock of the MQASK data transmitted. Employing the SRD, the closed loop timing recovery scheme performs the frequency-aided timing acquisition and achieve the synchronization at extremely high sampling frequency offset, which can be used in variable symbol rate MQASK receivers.

• Journal of Digital Contents Society
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• v.6 no.1
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• pp.41-48
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• 2005

In this paper, we propose and evaluate symbol timing recovery algorithm for S-DMT cable modern, which supports more channels and better quality symmetric mutimedia service over HFC network. We adopt timing recovery algorithm of PN sequence insertion in time domain and evaluate the performance of it in various noise channel such as AWGN, ISI, impulse. We verified that performance of this algorithm is depends on the channel noise environment and sampling clock offset and that over 10 dB degradation of Eb/No is occurred at the timing failure probability of $10^3$ in the composite noise channel of AWGN, ISI, and impulse in comparison with impulse noise-alone channel. finally, we verified that this algorithm showed good timing failure probability in case of sampling clock optimization was performed in advance.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1193-1196
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• 2003

This paper proposes a 2x oversampling method with a smart sampling for a clock and data recovery(CDR) circuit in a 2.5Gbps serial data link. In the conventional 2x oversampling method, the "bang-bang" operation of the phase detection produces a systematic jitter in CDR. The smart sampling in phase detection helps the CDR to remove the "bang-bang" operation and to improve the jitter performance. The CDR with the proposed 2x oversampling method is designed using Samsung 0.25${\mu}{\textrm}{m}$ process parameters and verified by simulation. Simulation result shows the proposed 2x oversampling method removes the systematic jitter.e systematic jitter.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.97-103
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• 2014

In this paper, a clock-data recovery using a 1/8-rate phase detector is proposed. The use of a conventional full or half-rate phase detector requires relatively higher frequency of a recovered clock, which is a burden on the design of a sampling circuit and a VCO. In this paper, a 1/8-rate phase detector is used to lower the frequency of the recovered clock and a linear equalizer is used as a input circuit of a phase detector to reduce the jitter of the recovered clock. A test chip fabricated in a 0.13-${\mu}m$ CMOS process is measured at 1.5-GHz for a 3-Gb/s PRBS input and 1.2-V power supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.69-74
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• 2003

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless Multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFTT after the getting the frequency, response of deducted channel from channel deducted of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of ${\pm}$ 1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.880-883
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• 2002

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFFT after the getting the frequency, response of deducted channel from channel deductor of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of $\pm$1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.