• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.225-230
• /
• 2013

In a bandpass sampling (BPS), the frequency of the sampler is lower than that of the signal being sampled. In this method, the baseband spectrum directly appears by the sampling operation, so that it is not necessary to use any frequency down-converter, which makes the receiver's hardware simpler. The second-order BPS uses two identical BPS samplers, of which sampling times are offset by each other. By exploiting the relationship between two sampled signals, it can be possible to cancel the aliased signal component or the interference due to the bandpass sampling. In order to cancel the interference, an interpolant filter is used to manipulate the phase characteristics of the BPS sampled signal. In this paper, it is introduced a multiband interpolant filter which can simultaneously cancel multiple interference signals that have been aliased from multiple frequency bands. In case of no need of interference cancellation, another method is suggested to enhance the signal quality by 3dB. A computer simulation has been performed, and the feasibility of the suggested methods has been verified.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.9
• /
• pp.13-19
• /
• 1999

This paper describes a design of an 8-bit 100KSPS 1mW CMOS A/D Converter. Using a novel systematic offset cancellation technique, we reduce the systematic offset voltage of operational amplifiers. Further, a new Gain amplifier is proposed. The proposed A/D Converter is fabricated with a $0.6{\mu}m$ single-poly triple-metal n-well CMOS technology. INL and DNL is within ${\pm}1LSB$, and SNR is about 43dB at the sampling frequency of 100KHz. The power consumption is $980{\mu}W$ at +3V power supply.

• Journal of Power Electronics
• /
• v.18 no.5
• /
• pp.1523-1535
• /
• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.4
• /
• pp.14-23
• /
• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.10a
• /
• pp.221-224
• /
• 2012

This paper presents a CMOS interface circuit for MEMS acceleration sensor. It consists of a capacitance to voltage converter(CVC), a second-order switched-capacitor (SC) integrator and comparator. A bandgap reference(BGR) has been designed to supply a stable bias to the circuit and a ${\Sigma}{\Delta}$ Modulator with chopper - stabilization(CHS) has also been designed for more suppression of the low frequency noise and offset. As a result, the output of this ${\Sigma}{\Delta}$ Modulator increases about 10% duty cycle when the input voltage amplitude increases 100mV and the sensitivity is x, y-axis 0.45v/g, z-axis 0.28V/g. This work is designed and implemented in a 0.35um CMOS technology with a supply voltage of 3.3V and a sampling frequency of 3MHz sampling frequency. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.5
• /
• pp.917-922
• /
• 2018

In the conventional interchannel interference self-cancellation (ICI-SC) schemes, the length of sampling window is the same as the symbol length of orthogonal frequency division multiplexing (OFDM). Thus, the number of complex operations to compute the interference coefficient of each subchannel is significantly increased. To solve this problem, we present an approximated mathematical model for the coefficients of ICI-SC schemes. Based on the proposed approximation, we analyze mean squared error (MSE) and computational complexity of the ICI-SC schemes with the length of sampling window. As a result, the presented approximation has an error of less than 0.01% on the MSE compared to the original equation. When the number of subchannels is 1024, the number of complex computations for the interference coefficients is reduced by 98% or more. Since the computational complexity can be remarkably reduced without sacrificing the self-cancellation capability, it is considered that the proposed approximation is very useful to develop an algorithm for the ICI-SC scheme.

• 한국정보통신설비학회:학술대회논문집
• /
• 2008.08a
• /
• pp.441-446
• /
• 2008

In this papers, a PLDRO(Phase Locked Dielectric Resonator Oscillator) is designed and implemented at the oscillator in which fundamental frequency is 18.3 GHz. The proposed PLDRO so as to improve the PLDRO of the general structure is designed to the goal of the minimize of the size and the performance improvement. Three VCO(Voltage controlled Oscillator) and the power combiner improved the output power. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is manufactured using a varactor diode to tune oscillating frequency electrically, and its phase is locked to reference frequency by SPD(Sampling Phase Detector). This product is fabricated on Teflon substrate with dielectric constant 2.2 and device is ATF -13786 of Ka-band using. This PLDRO generates an output power of 5.67 dBm at 18.3 GHz and has the characteristics of a phase noise of -80.10 dBc/Hz at 1 kHz offset frequency from carrier, the second harmonic suppression of -33 dBc. The proposed PLDRO can be used in Ka-band satellite applications

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.10
• /
• pp.1147-1158
• /
• 2008

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.125-126
• /
• 2006

본 논문에서는 주파수 오차가 큰 IEEE 802.15.4 시스템에서의 프레임 동기 및 주파수 추정기법을 제안한다. 주파수 오차의 영향을 제거하기 위해 coherent 방식이 아닌 non-coherent 방식의 프레임 동기가 요구된다. 차등 신호와 절대값을 이용하여 주파수 옵셋의 영향을 완벽히 제거한 프레임 동기를 제안하였다. 그리고 주파수 옵셋 추정의 분산을 줄이기 위한 over-sampling 주기의 주파수 옵셋 검출 기법을 제안하였다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.1
• /
• pp.69-74
• /
• 2003

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless Multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFTT after the getting the frequency, response of deducted channel from channel deducted of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of ${\pm}$ 1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.