• Proceedings of the KIEE Conference
• /
• 1987.07b
• /
• pp.1166-1169
• /
• 1987

A new analog-la-digital structure. called cyclic-parallel analog-to-digital(A/D) converter, has been developed for video applications. It consists of a M-bit parallel A/D converter, a digital-to-analog(D/A) converter, a differencing amplifier with gain of $2^M$ and two sample-and-hold circuits. In this structure, the input signal is circulated around the circuits K times, thereby converted into a MK-bit digital word. The proposed converter retains speed advantages of conventional series-parallel converters, with half reduced circuit components.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.975-978
• /
• 2003

본 논문에서는 비디오 신호 인터페이스를 위해 10비트 50MHz ADC 를 설계하였으며 DCL(digital-error correction logic)을 갖는 3-3-3-4 구조의 파이프라인 방식을 사용하였다. SHA(sample and hold amplifier)와 MDAC (multiplying digital-to-analog converter)에 쓰이는 증폭기는 높은 이득을 갖도록 gain-boosting 기법을 적용하였으며, 전력소모와 면적을 줄이기 위해 capacitor scaling 기법을 적용하였다. 본 ADC 는 0.35 μm double-poly four-metal n-well CMOS 공정으로 설계 및 제작하였으며, 전체 회로는 3.3V 단일 전원 전압에서 동작하도록 설계하였다. 측정 결과 5MHz 의 입력을 인가하였을 때 SNDR 은 56.7dB, 전체 전력 소모는 112mW 이며, 입출력 단의 패드를 포함한 전체 칩 면적은 2.6mm×2.6mm이다.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.10
• /
• pp.148-158
• /
• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• Journal of the Korean Society for Railway
• /
• v.10 no.2 s.39
• /
• pp.117-123
• /
• 2007

In this study, a ubiquitous sensor for condition monitoring of insulators and lightning arresters installed in power distribution lines and electric traction vehicles is presented. The sensor consists of two parts; a leakage current measurement and a lightning surge detection. Measured data are transmitted to a supervisory computer through ZigBee protocol based on IEEE 802.15.4. To detect leakage current, a window type Mn-ZCT is used and a low-noise amplifier with a gain of 60dB is designed, and this can measure leakage current in ranges of $100{\mu}A{\sim}5mA$. A sample-hold (S/H) and a Rogowski coil are injected to analyze the magnitude of surge current in ranges from 100A to 10kA with $8/20{\mu}s$-waveform.

• Journal of information and communication convergence engineering
• /
• v.10 no.1
• /
• pp.85-90
• /
• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.143-146
• /
• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.46 no.1
• /
• pp.76-81
• /
• 2009

A novel design method of time-interleaved subranging ADC is presented. We use the bisection method to let only half of comparators in typical subranging ADC working in every clock cycle. Thus, we are able to reduce the number of comparators by half. It is possible to reduce the die size. An example of 8-bit time-interleaved subranging ADC operates at 40MHz sampling rate and 1.8V supply voltage is demonstrated. The power consumption of the proposed circuit is only 10mV with SPECTRE simulation. Compared with the typical subranging ADC, our bisection method is able to reduce up to 40% in die size.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.9
• /
• pp.1709-1716
• /
• 2007

In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.65-73
• /
• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.11 s.353
• /
• pp.37-47
• /
• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.