• The Transactions of the Korea Information Processing Society
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• v.5 no.4
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• pp.995-1004
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• 1998

This paper presents an implementation of model checking tool for LTS process specification, which checks deadlock, livelock and reachability for the state and action. The implemented formal checker using modal mu-calculus is able to verify whether properties expressed in modal logic are true on specifications. We prove experimentally that it is powerful to check, safety and liveness for the state and action on LTS. The tool is implemented by $C^{++}$ language and runs on IBM PC under Windows NT.

• Korean Journal of Computational Design and Engineering
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• v.18 no.2
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• pp.83-92
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• 2013

IFC based open BIM has internationally developed as a solution for interoperability problem among different software applications. Despite much interest and effort, the open BIM technologies are rarely introduced to the construction industry and need more technical development for a practical application as well. This research aims to develop automated code checking modules for quality assurance process of BIM data. The research have analyzed domestic regulations focusing on super-tall buildings and developed open BIM-based code checking modules for the evacuation regulations. The modules are able to validate evacuation regulations such as installation of emergency elevator and fire safety zone. The authors expect to improve the process of BIM quality assurance and enhance the quality of BIM data by this research on automated checking system.

• Journal of the Society of Disaster Information
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• v.20 no.1
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• pp.60-68
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• 2024

Purpose: When designing plants and workplaces such as handling and using chemicals, a system that can automatically determine whether the design has been made in compliance with domestic safety management laws is established to shorten the review time and increase accuracy. Method: Safety design standards for chemical handling and use workplaces were investigated, and types and systems were derived that could automatically judge design errors by dividing the articles into semantic units. Result: An automatic design review method performed when designing a building was proposed, and a system that can review the safety design requirements required when designing a chemical handling business site through the development of a rule checker was proposed. After confirming whether the law is subject to application, the safety design rules are classified into semantic units through preprocessing. The classified results can be classified into four types, and the specifications, space, conditions, situations, and specific devices and facilities to reinforce safety were analyzed as representative types. It proposes a system that prepares a diagram for the safety design rule and allows it to be reviewed through the rule checker program.

• Proceedings of the KIEE Conference
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• 2007.04b
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• pp.91-94
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• 2007

The increased use of underground power distribution as opposed to overhead lines contributes to the aesthetics of the downtown areas. But there is an inherent risk of accidental electrocution should there be damage to the insulation of the cable because of heavy rain. Should a pedestrian make contact with this cable indirectly, via a man hole cover, electrocution could result. In this paper, we analyse electrical shock accident and checking results in this low-voltage handhole.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.633-640
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• 2007

As the embedded systems closely related with our living become complex by interoperating each other via internet, the safety issue of embedded systems begins to appear For checking safety properties of the system interactions, it is necessary to describe the system behaviors in formal methods and provide a systematic safety analysis technique. In this research, the behaviors of an embedded system are described by Labeled Transition Systems(LTS) and its safety properties are checked on the system model. For enhancing the existing compositional safety analysis technique, we perform the safety analysis techniques by checking the behavioral equivalence of the reduced model and a property model after reducing the system model in the viewpoint of the property.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.1
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• pp.396-413
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• 2017

Dynamically checking the integrity of software at run-time is always a hot and difficult spot for trusted computing. Control-flow integrity is a basic and important safety property of software integrity. Many classic and emerging security attacks who introduce illegal control-flow to applications can cause unpredictable behaviors of computer-based systems. In this paper, we present a software-based approach to checking violation of control flow integrity at run-time. This paper proposes a high-performance and low-overhead software control flow checking solution, control flow checking at virtual edges (CFCVE). CFCVE assigns a unique signature to each basic block and then inserts a virtual vertex into each edge at compile time. This together with insertion of signature updating instructions and checking instructions into corresponding vertexes and virtual vertexes. Control flow faults can be detected by comparing the run-time signature with the saved one at compile time. Our experimental results show that CFCVE incurs only 10.61% performance overhead on average for several C benchmark programs and the average undetected error rate is only 9.29%. Compared with previous techniques, CFCVE has the characteristics of both high fault coverage and low memory and performance overhead.

• Journal of Communications and Networks
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• v.16 no.4
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• pp.385-396
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• 2014

In this paper, we present a formal method for modeling and checking an enhanced version of the carrier sense multiple access with collision avoidance protocol related to the IEEE 802.11 MAC layer, which has been proposed as the standard protocol for wireless local area networks. We deal mainly with the distributed coordination function (DCF) procedure of this protocol throughout a sequence of transformation steps. First, we use the unified modeling language state machines to thoroughly capture the behavior of wireless stations implementing a DCF, and then translate them into the input language of the UPPAAL model checking tool, which is a network of communicating timed automata. Finally, we proceed by checking of some of the safety and liveness properties, such as deadlock-freedom, using this tool.

• Proceedings of the Safety Management and Science Conference
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• 2010.04a
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• pp.71-79
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• 2010

• Journal of Electrical Engineering and Technology
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• v.1 no.4
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• pp.513-519
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• 2006

As a very important part in development of the protocol, verifications for developed protocol specification are complementary techniques that are used to increase the level of confidence in the system functions by their specifications. Using the informal method for specifying the protocol, some ambiguity may be contained therein. This indwelling ambiguity in control systems can cause the occurrence of accidents, especially in the case of safety-critical systems. To clear the vagueness contained in the designed protocol, we use the LTS (Labeled Transition System) model to design the protocol for railway signaling. And then, we verify the safety and the liveness properties formally through the model checking method. The modal ${\mu}$-calculus, which is an expressive method of temporal logic, has been applied to the model checking method. We verify the safety and liveness properties of Korean standard protocol for railway signaling systems. To perform automatic verification of the safety and liveness properties of the designed protocol, a communication verification tool is implemented. The developed tools are implemented by C++ language under Windows XP. It is expected to increase the safety and reliability of communication protocol for signaling systems by using the developed communication verification tool.

• The KIPS Transactions:PartD
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• v.12D no.7 s.103
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• pp.931-936
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• 2005

There may be subtle errors in embedded software since its functionality is very complex. Thus formal verification for detecting them is very needed. Model checking is one of formal verification techniques, and SLAM is a well-known software model checking tool for verifying safety properties of embedded C program. In this paper, we develop a software model checker like SLAM for verifying embedded Java program Compared to SLAM, our tool allows to verify liveness properties as well as safety ones. As a result, we verify some desired properties in embedded Java program for controlling REGO robot.