• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.67-78
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• 2016

The emerging Spin-Transfer Torque RAM (STT-RAM) is a promising component that can be used to improve the efficiency as a result of its high storage density and low leakage power. However, the state-of-the-art STT-RAM is not ready to replace SRAM technology due to the negative effect of its write operations. The write operations require longer latency and more power than the same operations in SRAM. Therefore, a hybrid cache with SRAM and STT-RAM technologies is proposed to obtain the benefits of STT-RAM while minimizing its negative effects by using SRAM. To efficiently use of the hybrid cache, it is important to place write intensive data onto the cache. Such data should be placed on SRAM to minimize the negative effect. Thus, we propose a technique that optimizes placement of data in main memory. It drives the proper combination of advantages and disadvantages for SRAM and STT-RAM in the hybrid cache. As a result of the proposed technique, write intensive data are loaded to SRAM and read intensive data are loaded to STT-RAM. In addition, our technique also optimizes temporal locality to minimize conflict misses. Therefore, it improves performance and energy consumption of the hybrid cache architecture in a certain range.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• Proceedings of the Korean Magnestics Society Conference
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• 2007.05a
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• pp.62.1-62.1
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• 2007

• Proceedings of the Korean Magnestics Society Conference
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• 2008.12a
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• pp.4.1-4.1
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• 2008

• Proceedings of the Korean Society of Computer Information Conference
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• 2023.07a
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• pp.227-228
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• 2023

본 눈문에서는 안드로이드 플랫폼 기반의 스마트폰에서 장애 예술인 활동에 도움이 되는 애플리케이션을 설계 및 구현하였다. 이 애플리케이션의 특징은 TTS, STT 기능을 이용한다. STT 기능은 청각 장애인이 예술 작품을 올리면 작품에 대한 정보를 입력받고, TTS 활용하여 작품에 대한 설명을 음성으로 서비스하도록 구현한다. Naver Map을 사용하여 사용자가 전시회에 대한 위치를 등록하면 Naver Map을 통하여 전시회를 찾아올 수 있도록 길 안내 서비스를 구현한다.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.4
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• pp.274-282
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• 2016

This paper proposes code optimization techniques to reduce energy consumption of complex multimedia applications in a hybrid memory system with volatile dynamic random access memory (DRAM) and non-volatile spin-transfer torque magnetoresistive RAM (STT-MRAM). The proposed approach analyzes read/write operations for variables in an application. Based on the profile, variables with a high read operation are allocated to STT-MRAM, and variables with a high write operation are allocated to DRAM to reduce energy consumption. In this paper, to optimize code for real-life complicated applications, we develop a profiler, a code modifier, and compiler/link scripts. The proposed techniques are applied to a Fast Forward Motion Picture Experts Group (FFmpeg) application. The experiment reduces energy consumption by up to 22%.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.306.2-306.2
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• 2014

전자기기의 휴대성과 이동성이 강조되고 있는 현대사회에서 비휘발성 메모리는 메모리 산업에 있어 매우 매력적인 동시에 커다란 잠재성을 지닌다. 이미 공정의 한계에 부딪힌 Flash 메모리를 대신하여 10nm 이하의 공정이 가능한 상변화 메모리(Phase-Change Memory, PRAM), 스핀 주입 자화 반전 메모리(Spin Transfer Torque-Magnetic RAM, STT-MRAM), 저항 변화 메모리(Resistive Random Access Memory, ReRAM)가 차세대 비휘발성 메모리 후보로서 거론되고 있으며, 그 중에서도 ReRAM은 빠른 속도와 낮은 소비 전력, CMOS 공정 호환성, 그리고 비교적 단순한 3차원 적층 구조의 특성으로 인해 활발히 연구되고 있다. 특히 최근에는 질화물 또는 질소를 도핑한 산화물을 저항변화 물질로 사용하는 ReRAM이 보고되고 있는데, 이들은 동작전압이 낮을 뿐만 아니라 저항 변화(Resistive Switching, RS) 과정에서 일어나는 계면 산화를 방지할 수 있으므로 ReRAM의 저항 변화 재료로서 각광받고 있다. 그러나 Cell 단위의 ReRAM 소자를 Crossbar Array 구조에 적용시켰을 때 주변 Cell과의 저항 상태 차이로 인해 전류가 낮은 저항 상태(LRS)의 Cell로 흘러 의도치 않은 동작을 야기한다. 이와 같이 누설 전류(Leakage Current)로 인한 상호간의 간섭이 일어나는 Cross-talk 현상이 존재하며, 공정의 간소화와 집적도를 유지하면서 이 문제를 해결하는 것은 실용화하기에 앞서 매우 중요한 문제이다. 따라서, 본 논문에서는 Read 동작 시 발생하는 Cell과 Cell 사이의 Cross-talk 문제를 해결하기 위해 자가 정류 특성(Self-Rectifying)을 가지는 실리콘 질화물/알루미늄 질화물 이중층(Si3N4/AlN Bi-layer)으로 구성된 ReRAM 소자 구조를 제안하였으며, Sputtering 방법을 이용하여 제안된 소자를 제작하였다. 전압-전류 특성 실험결과, 제안된 구조에 대한 에너지 밴드 다이어그램 시뮬레이션 결과와 동일하게 Positive Bias 영역에서 자가 정류 특성을 획득하였고, 결과적으로 Read 동작 시 발생하는 Cross-talk 현상을 차단할 수 있는 결과를 확보하였다.

• Proceedings of the Korean Magnestics Society Conference
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• 2008.12a
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• pp.5.1-5.1
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• 2008

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.226-239
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• 2013

A number of systems have several on-chip memories with cache memory being one of them. Conventional cache memory consists of SRAM but the ratio of static energy to the total energy of the memory architecture becomes larger as the leakage power of traditional SRAM increases. Spin-Torque Transfer RAM (STT-RAM), which is a variety of Non-Volatile Memory (NVM), has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but it consumes too much writing energy. This study evaluated a wide range of energy consumptions of a two-level cache using NVM partially on a mobile processor. Through a number of experimental evaluations, it was confirmed that the use of NVM partially in the two-level cache effectively reduces energy consumption significantly.