• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2007년도 춘계학술발표회 초록집
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• pp.151-152
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• 2007

최근들어 Device 크기가 100nm 이하로 줄어듦에 따라 High Density Plasma Chemical Vapor Deposition(HDP-CVD) 기술로는 100nm 이하의 gap에 Aspect ratio가 6:1 이상 되는 STI(Shallow Trench Isolation) 구조를 Void 없이 채우는 것이 불가능해 지고 있다. 이를 극복하기 위하여 여러 방면으로 연구가 수행되어지고 있다. 그 방법 중의 하나인 Dep/Etch/Dep Cycle이 이번 연구에서 사용되었으며, 일반적인 HDP CVD보다 더 낮은 압력에서 증착과 식각이 수행되었다. 그 결과 다른 여러 방법들보다 좋은 막질을 얻을 수 있었으며, Gap fill 성능을 향상 시킬 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.344-345
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• 2012

The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권2호
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• pp.69-75
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• 2003

Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.239-242
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• 2004

We investigated the nanotopography impact on the post-chemical mechanical polishing (post-CMP) oxide thickness deviation(OTD) of ceria slurry with a surfactant. Not only the surfactant but also the slurry abrasive size influenced the nanotopography impact. The magnitude of the post-CMP OTD increased with adding the surfactant in the case of smaller abrasives, but it did not increase in the case of larger abrasives, while the magnitudes of the nanotopography heights are all similar. We created a one-dimensional numercal simulation of the nanotopography impact by taking account of the non-Prestonian behavior of the slurry, and good agreement with experiment results was obtained.

• Nuclear Engineering and Technology
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• 제56권8호
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• pp.3076-3083
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• 2024

In this work, single photon avalanche diodes (SPADs) were fabricated using the standard 180 nm complementary metal-oxide semiconductor process. Their small size of 15-16 µ m and low operating voltage made it possible to easily integrate them with readout circuits for compact on-chip sensors, particularly those used in the radiation sensor network of a nuclear plant. Four architectures were proposed for the SPADs, with a shallow trench isolation (STI) guard ring and different depletion regions designed to demonstrate the main performance parameters in each experimental configuration. The wide absorption region structure with PSD and a deep N-well could achieve a uniform electric field, resulting in a stable dark count rate (DCR). Additionally, the STI guard ring was implanted to mitigate the premature edge breakdown. A breakdown voltage was achieved for a low operating voltage of 10.75 V. The DCR results showed 286.3 Hz per ㎛² at an excess voltage of 0.04 V. A photon detection probability of 21.48% was obtained at 405 nm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.522-529
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• 2013

In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, $0.18{\mu}m$ 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.65-70
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• 2013

A 0.18-${\mu}m$ 3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving electrical overstress (EOS) robustness. The improved cell array consists of 20 GGNMOS, 4 inserted well taps, 2 end-well taps and shallow trench isolation (STI). Technology computer-aided design (TCAD) simulation results show that the inserted well taps and extended drain contact gate spacing (DCGS) is effective in preventing EOS failure, e.g. local burnout. Thermodynamic models for device simulation enable us to obtain lattice temperature distributions inside the cells. The peak value of the maximum lattice temperature in the improved GGNMOS cell array is lower than that in a conventional GGNMOS cell array. The inserted well taps also improve the uniformity of turn-on of GGNMOS cells. EOS test results show the validity of the simulation results on improvement of EOS robustness of the new GGNMOS I/O cell array.

• 전기전자학회논문지
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• 제27권4호
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• pp.644-649
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• 2023

DRAM(Dynamic Random Access Memory) 스케일링 과정에서 발생하는 셀간 거리의 감소에 따라 STI(Shallow Trench Isolation)두께 감소는 문턱이하 누설이 증가되는 패싱워드라인 효과를 유발한다. 인접한 패싱워드라인에 인가된 전압으로 인한 문턱이하누설 전류의 증가는 데이터 보존시간에 영향을 주며, 리프레시의 동작 횟수가 증가되어 DRAM의 소비 전력을 증가시키는 요인이 된다. 본 논문에서는 TCAD Simulation을 통해 패싱워드라인 효과에 대한 원인을 확인한다. 결과적으로, 패싱워드라인 효과가 발생하는 DRAM 동작상황을 확인하고, 이때 패싱워드라인 효과로 인해 전체 누설전류의 원인에 따른 비중이 달라지는 것을 확인하였다. 이를 통해, GIDL(Gate Induced Drain Leakage)에 의한 누설전류뿐만 아니라 문턱이하 누설전류를 고려의 필요성을 확인하며 이에 따른 DRAM 구조의 개선 방향의 지침이 될 수 있다.