• Journal of Power Electronics
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• v.14 no.5
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• pp.1057-1068
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• 2014

Phase-locked loops (PLL) based on the synchronous reference frame (SRF-PLL) have recently become the most widely-used for grid synchronization in three phase grid-connected inverters. However, it is difficult to study their performance since they are nonlinear systems. To estimate the performances of a SRF-PLL, a canonical small-signal linearized model has been developed in this paper. Based on the proposed model, several significant specifications of a SRF-PLL, such as the capture time, capture rang, bandwidth, the product of capture time and bandwidth, and steady-state error have been investigated. Finally, a noise model of a SRF-PLL has been put forward to analyze the noise rejection ability by computing the SNR (signal-to-noise ratio) of a SRF-PLL. Several simulation and experimental results have been provided to verify and validate the obtained conclusions. Although the proposed model and analysis method are based on a SRF-PLL, they are also suitable for analyzing other types of PLLs.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.508-509
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• 2012

그리드 연계 인버터의 주파수 위상 동기를 위해 사용하는 SRF PLL의 입력함수를 Vq및 Vd 전압을 복합적으로 사용하여 응답특성을 개선시켰다. 기존의 SRF PLL에서 Vq만을 이용한 구조는 위상범위 [$-{\pi}/2$, ${\pi}/2$]에서만 선형 동작이 가능하지만, 제안된 구조는 $2{\pi}$ 영역 모두에서 선형 동작이 가능토록 하였다. 시뮬레이션으로 위상차 ${\pi}$에서 기존 SRF PLL의 부동작을 확인하고 제안된 방법의 속응성을 보였다.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.509-510
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• 2016

본 논문은 계통연계형 인버터의 위상추종기법인 SRF-PLL을 모델링하고, FPGA에 구현하기 위해 System Generator를 이용하여 설계하였다. SRF-PLL의 비례-적분 이득은 소신호 해석을 하여 일반화를 통해 입력전압의 크기에 관계없이 적용가능하며, 주파수 응답에서 65도 위상여유를 갖는 안정한 이득을 산정하였다. FPGA 구현을 위해 MATLAB/SIMULINK와 연동 가능한 System Generator를 이용하여 SRF-PLL을 모델링하였으며, MATLAB 기반의 시뮬레이션과 실험을 통하여 위상추종 특성을 분석하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.2
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• pp.134-141
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• 2009

The new method is proposed to improve the dynamics of the phase angle detector during abrupt voltage dip caused by a grid fault. Usually, LPF(low pass filter) is used in the feedback loop of SRF(Synchronous Reference Frame) - PLL (Phase Locked Loop) system because the measured grid voltage contains harmonic distortions and sensor noises. A better transient response can be obtained with the proposed design method for SRF-PLL by the analysis of linearized model of the PLL system including LPF. Furthermore, in the proposed method, the controller gain and LPF cut-off frequency are changed from normal value to transient value when the voltage disturbance is detected. This paper shows the feasibility and the usefulness of the proposed methods through the computer simulation and the experiment.

• Journal of Power Electronics
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• v.16 no.1
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• pp.18-26
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• 2016

This paper proposes a compensation algorithm for reducing a specific ripple component on synchronous reference frame phase locked loop (SRF-PLL) in grid-tied single-phase inverters. In general, SRF-PLL, which is based on all-pass filter to generate virtual voltage, is widely used to estimate the grid phase angle in a single-phase system. In reality, the estimated grid phase angle might be distorted because the phase difference between actual and virtual voltages is not 90 degrees. That is, the phase error is caused by the difference between cut-off frequency of all-pass filter and grid frequency under grid frequency variation. Therefore, the effects on phase angle and output current attributed to the phase error are mathematically analyzed in this paper. In addition, the proportional resonant (PR) controller is adapted to reduce the effects of phase error. The validity of the proposed algorithm is verified through several simulations and experiments.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.219-220
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• 2014

기존의 SRF-PLL방법은 구현이 간단하고 정상전원에서 위상각 추정 성능이 우수하지만 불평형 전원하에서 위상각 추정 성능이 저하된다. 본논문에서는 상간전압의 위상변화, 상전압의 크기변동 및 오프셋이 발생된 불평형 전원하에서 변동된 값들을 실시간으로 보상하여 위상각을 검출하는 재귀형 최소 자승법을 이용한 SRF-PLL방법을 제안한다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.10
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• pp.73-82
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• 2015

This paper proposes an ripple reduction algorithm and analyzes the effects of offset and scale errors generated by voltage sensor while measuring grid voltage in grid-tied single-phase inverters. Generally, the grid-connected inverter needs to detect the phase angle information by measuring grid voltage for synchronization, so that the single-phase inverter can be accurately driven based on estimated phase angle information. However, offset and scale errors are inevitably generated owing to the non-linear characteristics of voltage sensor and these errors affect that the phase angle includes 1st harmonic component under using SRF-PLL(Synchronous Reference Frame - Phase Locked Loop) system for detecting grid phase angle. Also, the performance of the overall system is degraded from the distorted phase angle including the specific harmonic component. As a result, in this paper, offset and scale error due to the voltage sensor in single-phase grid connected inverter under SRF-PLL is analyzed in detail and proportional resonant controller is used to reduce the ripples caused by the offset error. Especially, the integrator output of PI(Proportional Integral) controller in SRF-PLL is selected as an input signal of the proportional resonant controller. Simulation and experiment are performed to verify the effectiveness of the proposed algorithm.

• Proceedings of the KIPE Conference
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• 2008.10a
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• pp.71-73
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• 2008

급변하는 전압 변동 상황에서 전력 제어를 수행하기 위해서 기존의 동기좌표 위상각 검출 제어기의 특성을 보완할 수 있는 방법을 제시하였다. 실질적인 SRF (Synchronous Reference Frame) - PLL(Phase Locked Loop) 시스템에서 계통 전압은 이상적이지 않고 센서 노이즈 등의 저감을 위하여 측정된 전압에 LPF(Low Pass Filter)를 사용하고 있는데 이러한 LPF의 특성을 고려하여 위상각 제어기의 PI게인을 설정하는 방법을 제시하였으며 가변 게인과 LPF 차단주파수 변동방식을 이용하여 전원 전압 사고의 종류에 따라 위상과 전압이 급변하는 경우에 대하여 시뮬레이션과 실험을 통해 제한된 방법으로 동특성이 개선되고 원하는 응답속도로 설계가 가능함을 보였다.

• Proceedings of the KIPE Conference
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• 2009.11a
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• pp.302-304
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• 2009

Phase Locked Loop(PLL) 시스템은 UPS, 전력용 능동필터, PWM 정류기 등 여러 전력변환 장비에서 사용되어 왔다. 특히 계통에 연계된 능동 전력변환 시스템은 계통과의 동기화를 위해 위상각의 정확한 정보가 필요하며 PLL 시스템을 사용하여 측정한다. 실제 계통의 위상각과 추출된 위상각 사이의 오차는 기준 전류나 전압에 더 큰 고조파를 야기한다. 본 논문은 계통 고장에 강인한 PLL 시스템의 제어기를 제안한다.

• Journal of Power Electronics
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• v.11 no.3
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• pp.369-374
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• 2011

Usually, a LPF (low pass filter) is used in the feedback loop of a SRF (synchronous reference frame) - PLL (phase locked loop) system because the measured grid voltage contains harmonic distortions and sensor noises. In this paper, it is shown that the cut-off frequency of the LPF should be designed to suppress the harmonic ripples contained in the measured voltage. Also, a new design method for the loop gain of the PI-type controller in the SRF-PLL is proposed with consideration of the dynamics of the LPF. As a result, a better transient response can be obtained with the proposed design method. The LPF frequency and the PI controller gain are designed in coordination according to the steady state and dynamic performance requirements. Furthermore, in the proposed method, the controller gain and the LPF cut-off frequency are changed from their normal value to a transient value when a voltage disturbance is detected. This paper shows the feasibility and usefulness of the proposed methods through the computer simulations and experimental results.