• Journal of the Korea Computer Industry Society
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• v.2 no.12
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• pp.1533-1540
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• 2001

In this paper, we described extraction method of electrical parameters and modeling method of PCB nets on PCB design process. To analyze electrical characteristics of real PCB structure, we selected a cache memory system as an experimental board and designed 6 layer PCB substrate. For extraction of the electrical parameters, we divided circuit elements into the components of conductor types which are wires, via holes, BGA balls etc. and combined the calculated value by real net structure to modeling the PCB nets. We analyzed the electrical characteristics of the PCB nets with the simulation tools of SPICE and XNS. The simulation analysis has shown that the maximum signal delay was 2.6ns and the maximum crosstalk noise was 281 mV and we found that the designed substrate was adequate to system specification.

• 전자공학회논문지 IE
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• v.48 no.4
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• pp.13-18
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• 2011

In this paper, we have examined electrical characteristics of LDO regulator according to the process variation using a 1 ${\mu}m$ 20 V high voltage CMOS process. The electrical analysis of LDO regulator have been performed with three kind of SPICE parameter sets (Typ : typical, FF : fast, SS : slow) by process variation which cause change of SPICE parameter such as threshold voltage and effective channel length of MOS devices. From simulation results, we confirmed that in case of SS type SPICE parameter set, the LDO regulator has 3.6 mV/V line regulation, 0.4 mV/mA load regulation and 0.86 ${\mu}s$ output voltage settling time. And in case of Typ type SPICE parameter set, the LDO regulatorhas 4.2 mV/V line regulation, 0.44 mV/mA load regulation and 0.62 ${\mu}s$ output voltage settling time. Finally, in the FF type SPICE parameter set, the LDO regulator has 7.0 mV/V line regulation, 0.56 mV/mA load regulation and 0.27 ${\mu}s$ output voltage settling time.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.8-16
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• 1999

This paper presents a new simulation-based analog cell synthesis approach with improved simulation efficiency For the hierarchical synthesis of analog cells we developed the sub-circuit optimizers such as current mirror and differential input stage. Each sub-circuit optimizer can be used for synthesis of analog cells such as OTA(operational transconductance amplifier), 2-stage OP-AMP and comparator. To reduce the time spending of the simulation-based synthesis we propose 2-stage searching scheme and simulation data reusing scheme. With those schemes the synthesis time spending of OTA was reduced from 301.05sec to 56.52sec by 81.12%. Since our synthesis system doesn't need other additional physical parameters except SPICE parameters, and is independent of the process and its model level, the time spending to port to other process is minimized. We synthesized OTA and 2-stage OP-AMP respectively with our approach to show its usefulness.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.47-50
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• 2000

DC Gummel-Poon SPICE model parameter extraction program has been implemented. This program extracts the parameters from measured data using Levenberg-Marquardt algorithm. Measured data consist of forward and reverse Gummel plot, forward and reverse output characteristics and RE and RC measurements.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.943-946
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• 2003

This paper proposes new SPICE Macro-Model of MTJ(Magnetic Tunnel Junction). This Macro-Model has five I/O terminals, reproduces MR characteristics including hysteresis and behaves correctly to time varying input signals. Furthermore, this Model can be easily modified to various MTJs with different characteristics by simply varying internal parameters.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.314-317
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• 2000

In order to analyze the characteristics of complicated TFT-LCD (Thin Film Transistor-Liquid Crystal Display) circuits, it is indispensible to use simulation programs. In this study, we present a systematic method of extracting the input parameters of poly-Si TFT for Spice simulation. This method is applied to two different types of poly-Si TFTs fabricated in our group with good results. Among the Spice simulators, Pspice has the graphic user interface feature making the composition of complicated circuits easier. We added successfully a poly-Si TFT model on the Pspice simulator, which would contribute to efficient simulations of poly-Si TFT-LCD pixels and arrays.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1532-1535
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• 1987

In this paper, we propose the algorithm for mask level simulation. The circuit parameters were extracted from the photomask data in format of bitmap. The extracted circuit parameter was transformed into the input file format of SPICE-16. And then the simulation of mask pattern data was carried out the SPICE-16. Thus the error operation of IC due to the mistake of photomask pattern could be prevented.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.545-546
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• 2006

The improved model that external capacitances are connected to a conventional BSIM3v3 RF Macro model with Rg and Rsub is developed in this paper. The extracted external capacitances and resistances are modeled by scalable fitting equations. The modeled S-parameters of $0.13{\mu}m$ NMOSFET agree well with measured ones from 10MHz to 10GHz, verifying the accuracy of the improved model.

• Journal of electromagnetic engineering and science
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• v.15 no.4
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• pp.258-265
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• 2015

A de-embedding method for multiport networks, especially for coupled odd interconnection lines, is presented in this paper. This method does not require a conversion from S-parameters to T-parameters, which is widely used in the de-embedding technique of multiport networks based on cascaded simple two-port relations, whereas here, we apply an operation to the S-matrix to generate all the uncoupled and coupled coefficients. The derivation of the method is based on the relations of incident and reflected waves between the input of the entire network and the input of the intrinsic device under test (DUT). The characteristics of the intrinsic DUT are eventually achieved and expressed as a function of the S-parameters of the whole network, which are easily obtained. The derived coefficients constitute ABCD-parameters for a convenient implementation of the method into cascaded multiport networks. A validation was performed based on a spice-like circuit simulator, and this verified the proposed method for both uncoupled and coupled cases.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.1943-1950
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• 2009

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.