• Journal of Sensor Science and Technology
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• v.14 no.6
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• pp.387-394
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• 2005

In order to design SOI CMOS image sensors, SOI MOSFET model parameters were extracted using the equation of bulk MOSFET model parameters and were optimized using SPICE level 2. Simulated I-V characteristics of the SOI NMOSFET using the extracted model parameters were compared to the experimental I-V characteristics of the fabricated SOI NMOSFET. The simulation results agreed well with experimental results. A unit pixel for SOI CMOS image sensors was designed and was simulated for the PPS, APS, and logarithmic circuit using the extracted model parameters. In these CMOS image sensors, a nano-wire MOSFET photodetector was used. The output voltage levels of the PPS and APS are well-defined as the photocurrent varied. It is confirmed that SOI CMOS image sensors are faster than bulk CMOS image sensors.

• Journal of Sensor Science and Technology
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• v.18 no.2
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• pp.128-134
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• 2009

Integrated circuit of a new neuron chain with a synapse function for Hodgkin-Huxley model which is a good electrical model about a real biological neuron is implemented in a $0.5{\mu}m$ 1 poly 2 metal CMOS technology. Pulse type neuron chain consist of series connected current controlled single neurons through synapses. For the realization of the single neuron, a pair of voltage mode oscillators using operational transconductance amplifiers and capacitors is used. The synapse block which is a connection element between neurons consist of a voltage-current conversion circuit using current mirror. SPICE simulation results of the proposed circuit show 160 mV amplitude pulse output and propagation of the signal through synapses. Measurements of the fabricated pulse type neuron chip in condition of ${\pm}2.5\;V$ power supply are shown and compared with the simulated results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.463-470
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• 2014

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.114-121
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• 2001

A circuit model for active-controlled field emitter array(ACFEA) as an electron source of active-controlled field emission display(ACFED) has been proposed. The ACFEA with hydrogenated amorphous silicon thin-film transistor(a-Si:H TFT) and Spindt-type molibdenum tips (Spindt-Mo FEA) has been fabricated monolithically on the same glass. A-Si:H TFT is used as a control device of field emitters, resulting in stabilizing emission current and lowering driving voltage. The basic model parameters extracted from the electrical characteristics of the fabricated a-Si:H TFT and Spindt-Mo FEA were implemented into the ACFEA model with a circuit simulator SPICE. The accuracy of the equivalent circuit model was verified by comparing the simulated results with the measured one through DC analysis of the ACFEA. The transient analysis of the ACFEA showed that the gate capacitance of FEA along with the drivability of TFT strongly affected the response time. With the fabricated ACFEA, we obtained a response time of 15$mutextrm{s}$, which was enough to make 4bit/color gray scale with the pulse width modulation (PWM).

• Journal of Internet Computing and Services
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• v.10 no.5
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• pp.195-209
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• 2009

The embedded software has been become more important than the hardware in mobile systems in ubiquitous society. The improvement models such as CMMI(Capability Maturity Model Integration) and SPICE(Software Process Improvement and Capability dEtermination) are used to improve the quality of software in general systems. Software process improvement is also necessary for mobile embedded software development to improve its quality. It is not easy to apply the general software improvement model to the mobile embedded software development due to the high cost effectiveness and heavy process. On the other hand, XP has the characteristics on focused communications with customers and iteration development. It is specially suitable for mobile embedded software development as depending on customer's frequent requirement changes and hardware attributes. In this paper, we propose a framework for development small process improvement based XP(eXtreme Programming)'s practice in order to accomplish CMMI level 2 or 3 in mobile embedded software development at the small organizations. We design and implement the Mobile Embedded Software Process Improvement System(MESPIS) to support process improvement. We also suggest the evaluation method for the mobile embedded software development process improvement framework with CMMI coverage check by comparing other process improvement model. In the future, we need to apply this proposed framework to real project for practical effectiveness and the real cases quantitative. It also include the enhance the functionality of MESPIS.

• Journal of Technology Innovation
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• v.23 no.3
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• pp.287-316
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• 2015

The trend of R&D in automotive electronics industry is shifting towards ECU(Electronic Control Units) based on softwares which requires technology convergence to accommodate customers' requests on safety and convenience. The trend requires systemized R&D paradigm which reflects increased role of softwares. As the softwares became the core components in automotive innovation, there has been wide range of efforts to introduce software R&D processes and methodologies such as CMMI, A-SPICE and ISO-26262 etc. However, R&D departments in the industry fields are confronted with conflicts which arise from discrepancies among the individual process. In this study, we focus on suggesting our integrated and systematic R&D process with the aim of alleviating the conflicts and confusions. For this purpose, we analyze the cases of Korean automotive electronics companies to compare various R&D processes in the field and their relationships. Based on the analysis, we derive and suggest our model of R&D process which effectively integrate ISO/TS-16949 for manufacturing quality and CMMI, A-SPICE, ISO-26262 for system with softwares.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.8-15
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• 2002

We optimally designed the VCO(voltage-controlled oscillator) with spiral inductor using the MOSIS HP 0.5${\mu}{\textrm}{m}$ CMOS process. With the developed SPICE model of spiral inductor, the quality factor of spiral inductor was maximized at the operating frequency by varying the layout parameters, e.g., metal width, number of turns, radius, space of the metal lines. For the operation frequency of 2㎓, the inductance of about 3nH, and the MOSIS HP 0.5 CMOS process with the metal thickness of 0.8${\mu}{\textrm}{m}$, oxide thickness of 3${\mu}{\textrm}{m}$, the optimal width of metal lines is about 20${\mu}{\textrm}{m}$ for the maximum Quality factor. With the optimized spiral inductor, the VCO with LC tuning tank was designed, fabricated and measured. The measurements were peformed on-wafer using the HP8593E spectrum analyzer. The oscillation frequency was about 1.610Hz, the frequency variation of 250MHz(15%) with control voltage of 0V - 2V, and the phase noise of -108.4㏈c(@600KHz) from output spectrum.

• Journal of Information Technology Applications and Management
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• v.9 no.3
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• pp.113-127
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• 2002

The effort for software process improvement is lately surging its interest though it does not satisfy both developer and receiver In terms of low productivity, quality, delay and increasing cost. According to current research, software process improvement contributes to improvement of productivity, its Duality, reduction of development time and cost, and the prediction of the time limit for delivery, which means software process improvement affects competitive advantage among developers. The latest research is whether the investment for information technology substantially had effect on improvement of productivity. That is, software process improvement and maturity of software industries has influence upon economic efficiency and as a result, it plays an important role in whole industries. This research is that how does software process improvement using CMM (Capability Maturity Model) and SPICE (Software Process Improvement and Capability dEtermination) have a effect on factors of software engineering, and how does it have influence upon competitive advantage among SI firms. For this research, reusability, customizability, participation, and review & inspection are set to independent variable and process flexibility and process predictability are set to mediate Variable. Finally, competitive advantage among SI firms Is set to dependent variable. The targets for survey are laborers who work for SI firms. The result of this research is as follows: 1 ) Reusability, Customizability and participation is not rejected but review and Inspection is rejected in process flexibility which has significant level 0.05. 2) Reusability, Customizability and participation is not rejected but review and inspection Is rejected in process predictability which has significant level 0.05. 3) Process flexibility is not rejected and process predictability Is rejected in the competitive advantage of 51 industries which has significant level 0.05

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.64-71
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• 2014

Multiplier performs a complex arithmetic operation in various signal processing algorithms such as multimedia and communication system. The multiplier also suffers from its relatively large signal propagation delay, high power dissipation, and large area requirement. This paper presents memristor-CMOS based reconfigurable multiplier reducing area occupation of the multiplier circuitry and increasing compatibility using optimized bit-width for various applications. The performance of the memristor-CMOS based reconfigurable multiplier are estimated with memristor SPICE model and 180 nm CMOS process under 1.8 V supply voltage. The circuit shows performance improvement of 61% for area, 38% for delay and 28% for power consumption respectively compared with the conventional reconfigurable multipliers. It also has an advantage for area reduction of 22% against a twin-precision multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.1-9
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• 2011

Memristor is a portmanteau of "memory resistor". The resistance of memristor is changed depends on the history of electric charge that passed through the device and it is able to memorize the last resistance after turning off the power supply. This paper presents this device that has a high chance to be the next generation of commercial non-volatile memory and its behavior modeling using SPICE simulation. The memristor MOS content addressable memory (M_CAM) is also designed and simulated using the proposed behavioral model. The proposed M_CAM unit cell area and power consumption show an improvement around 40% and 96%, respectively, compare to the conventional SRAM based CAMs. The M_CAM layout is also implemented using 0.13${\mu}m$ mixed-signal CMOS process under 1.2 V supply voltage.