• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.439-442
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• 2004

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.59-64
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• 2017

As the demand on displays increases, new thin-film transistors such as metal oxide transistor are continuously being invented. When designing a circuit consisting of such new transistors, a new transistor model based on proper charge transport mechanisms is needed for each of them. In this paper, a modeling framework which enables to choose charge transport mechanisms that are limited to certain operation regions and assemble them into a transistor model instead of making an integrated transistor model dedicated to each transistor. The framework consists of a graphic user interface to choose charge transport models and a current calculation part, which is also implemented in AIM-SPICE for circuit simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.54-65
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• 1999

As the integration ratio and operating speed increase, it has become an important problem to estimate the dissipated power during the design procedure to reduce th TTM(time to market). This paper proposed a prediction model for the maximum dissipated power of a CMOS logic gate. This model uses a calculating method. It was constructed by including the characteristics of MOSFETs, the operational characteristics of the gate, and the characteristics of the input signals. As the construction procedure, a maximum power estimation model for CMOS inverter was formed first, And then, a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. We designed several CMOS gates in layout level with $0.6{\mu}m$ design rule to apply both to HSPICE simulation and to the proposed models. The comparison between the two results showed that the gate conversion model and the power estimation model had within 5% and 10% of the relative errors, respectively. Those values show that the proposed models have sufficient accuracies. Also in calculation time, the proposed models were more than 30 times faster than HSPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.59-68
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• 1999

The timing characteristics of an ASIC are analyzed based on the propagation delays of each gate and interconnect wire. The gate delay can be modeled using the two-dimensional delay table whose index variables are the input transition time and the output load capacitance. The AWE technique can be adopted as an algorithm to compute the interconnect delay. Since these delays are affected by the interaction to the two-dimensional delay table and the AWE technique. A method to model this effect has been proposed through the effective capacitance and the gate driver model under the assumption of single driving gate. This paper presents a new technique to handle the multiple CMOS gates driving interconnect wire by extending previous approach. This technique has been implemented in C language and applied to several interconnect circuits driven by multiple CMOS gates. In most cases, we found a few tens of speed-up and only a few percents of errors in computing both of gate and interconnect delays, compared to SPICE.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.226-235
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• 1999

To investigate SPICE noise model and the behavior of its parameters, 1/f noise of NMOS devices fabricated by BiCMOS process is measured and compared to the various noise models and measured results. For the long channel devices, bias dependence of the drain current noise power spectral density $S_{Id}$ of NMOS is similar to the previous results. Equivalent gate noise power spectral density $S_{Vg}$ shows weak dependence on the gate and drain voltages in long channel NMOS as the previous results. However, it is shown that most of published noise models are difficult to apply to short channel devices. Therefore, in this study, with comparison of our experimental results, we have tried to find the model of 1/f noise, appropriate for our NMOS device fabricated by BiCMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.1-5
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• 2000

This paper deals with the modeling and analysis of the high voltage flyback transformer (HVFBT) often utilized in small-sized high voltage DC power supplies. The parasitic capacitance of th HVFBT with the large turns of the secondary winding causes the undesirable parasitic resonance in the transient state which produces the high current stress and limits the switching frequency of the converter. In order to analyze this phenomenon the equivalent circuit model including the parasitic capacitance is derived and the frequency characteristics are provided. The parasitic resonance in the switching states is also investigated based on this equivalent circuit model. The derived model and analysis is finally validated through the SPICE simulation and experiments.

• Journal of the Korean Society of Safety
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• v.29 no.5
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• pp.22-28
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• 2014

This study is compare to model-based analysis and experimental data of the response characteristic of interior impulse noise. Interior impulse noise and the pressure response characteristics of the building structure on its analysis are presented the impulse pressure acting on the rear wall 90 N-sec. The force acting on the wall $CFD^{{+}{+}}$ which are compared measurement and simulation analysis. Results of simulation and measurement data were shown. In this study, a high dimension of the degree of virtual space in the numerical space of the lesser degree in order to calculate folding method was applied. The results of this study contribute safety evaluation and model development for the interior impulse noise that affects the basic data for the interior impulse noise model validate for the physical quantity prediction.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.129-133
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• 1997

A circuit model for a field emission triode has been proposed. The model parameters have been extracted from he fabricated silicon tip array and verified by comparing with the results simulated by circuit simulator(SPICE). The cut-off frequency can be calculated from the parametric capacitance and the transconductance values extracted from measurements. For the field emission triode, the capacitance of 3.45fF/tip and the transconductance of 0.94nS/tip have been measured under the emission current of 4.1nA/tip. From these values, the cut-off frequency is predicted to be 43 kHz but th measured one came out to be 6 kHz. because o the parasitic capacitance components.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.320-323
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• 2000

In the resent years, the Thin Film Transistor Liquid Crystal Display(TFT-LCD) have trend toward larger panel sizes and higher spatial and/or gray-scale resolution. In this trend, Because of its low field effect mobility, a-Si TFT is change to poly-Si TFT. In this paper, both effective-medium model of poly-Si TFTs and empirical capacitance model are applied to Pixel Design Array Simulation Tool (PDAST) and the pixel characteristics of TFT-LCD array were simulated, which were compared with the results calculated by Aim-Spice.