• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.310-312
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• 1994

A partial shunt regulator (PSR) which is the power regulator of KOREASAT is modeled. The modeling of the PSR consist of solar array, power circuit, controller. and load models. To realize simple structure. a voltage source of the PSR controller is used the output voltage of the PSR. The model of the PSR has very complex structure with two additional coupled feedback loops. The complex model is simplified to a simple meaningful model with only main feedback control loop. The proposed model is compared to a PSR model with DC voltage source at the PSR controller. The proposed PSR model is verified by comparing the model with SPICE simulation for small signal analysis.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.21-29
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• 1998

As silicon geometry shrinks into deep submicron and the operating speed icreases, higher accuracy is required in the analysis of the propagation delays of the gates and interconnects in an ASIC. In this paper, the driving characteristics of a CMOS gate is represented by a gatedriver model, consisting of a linear resistor $R_{dr}$ and an independent ramp voltage source $V_{dr}$ . We drivered $R_{dr}$ and $V_{dr}$ as the functions of the timing data representing gate driving capability and an effective capacitance $C_{eff}$ reflecting resistance shielding effect by interconnet circuits. Through iterative applications of these equations and AWE algorithm, $R_{dr}$ , $V_{dr}$ and $C_{eff}$ are comuted simulataneously. then, the gate delay is decided by $C_{eff}$ and the interconnect circuit delay is determined by $R_{dr}$ and $V_{dr}$ . this process has been implemented as an ASIC timing analysis program written in C language and four real circuits were analyzed. In all cases, we found less than 5% of errors for both of gate andinterconnect circuit delays with a speedup factor ranging from a few tens to a few hundreds, compared to SPICE.SPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.20-28
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• 2006

A new TWA(Traveling-wave-based Waveform Approximation)-based signal integrity verification method for practical interconnect layout structures which are composed of non-uniform RLC lines with various discontinuities is presented. Transforming the non-uniform lines into virtual uniform lines, signal integrity of the practical layout structures can be very efficiently estimated by using the TWA-technique. It is shown that the proposed technique can estimate the signal integrity much more efficiently than generic SPICE circuit model with 5% timing error and 10% crosstalk error.

• Journal of Sensor Science and Technology
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• v.23 no.4
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• pp.284-289
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• 2014

In this paper, modeling of a gate/body-tied (GBT) PMOSFET photodetector with built-in transfer gate is performed. It can control the photocurrent with a high-sensitivity. The GBT photodetector is a hybrid device consisted of a MOSFET, a lateral BJT, and a vertical BJT. This device allows for amplifying the photocurrent gain by $10^3$ due to the GBT structure. However, the operating parameters of this photodetector, including its photocurrent and transfer characteristics, were not known because modeling has not yet been performed. The sophisticated model of GBT photodetector using a process simulator is not compatible with circuit simulator. For this reason, we have performed SPICE modeling of the photodetector with reduced complexity using Cadence's Spectre program. The proposed modeling has been demonstrated by measuring fabricated chip by using 0.35 im 2-poly 4-metal standard CMOS technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.145-150
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• 1998

8$\times$8 bit scaled SONOSFET NAND type flash EEPROM that shows better characteristics on cell density and endurance than NOR type have been designed and its electrical characteristics are verified with computer aided simulation. For the simulation, the spice model parameter was extracted from the sealed down SONOSFET that was fabricated by $1.5mutextrm{m}$ topological design rule. To improve the endurance of the device, the EEPROM design to have modified Fowler-Nordheim tunneling through the whole channel area in Write/Erase operation. As a result, it operates Write/Erase operation at low current, and has been proven Its good endurance. The NAND type flash EEPROM, which has upper limit of V$_{th}$, has the upper limit of V$_{th}$ as 4.5V. It is better than that of floating gate as 4V. And a EEPROM using the SONOSFET without scaling (65$\AA$-l65$\AA$-35$\AA$), was also designed and its characteristics have been compared. It has more possibliity of error from the V$_{th}$ upper limit as 4V, and takes more time for Read operation due to low current. As a consequence, it is proven that scaled down SONOSFET is more pertinent than existing floating gate or SONOSFET without scaling for the NAND type flash EEPROM.EPROM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.1-6
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• 2011

Low-power logic gates, i.e. inverter, NAND, and NOR, are proposed employing only n-channel oxide thin film transistors (TFTs). The proposed circuits were designed to prevent the pull-up and pull-down switches from being turned on simultaneously by using asymmetric feed-through and bootstrapping, thereby exhibited same output voltage swing as the input signal and no static current. The inverter is composed of 5 TFTs and 2 capacitors. The NAND and the NOR gates consist of 10 TFTs and 4 capacitors respectively. The operations of the logic gates were confirmed successfully by SPICE simulation using oxide TFT model.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.317-320
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• 2003

As a convenient means for the characterization of the wall voltage and wall charge of AC PDPs during the sustain period, an equivalent circuit model for AC PDPs is presented. The equivalent circuit model for AC PDPs consists of capacitors and thyristors. The equivalent circuit model is based on the physical structure of the AC PDP and the I-V characteristic of the discharge space. This equivalent circuit model can be easily implemented in the standard simulators such as SPICE and can easily simulate the variation of the current, charge and voltage involved in AC PDPs as the supply voltage varies.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.561-564
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• 1998

This paper describes a performance degradation of static type input buffer due to the device degradation in menory devices using $0.8\mu\textrm{m}$ CMOS process. experimental results shows that the degradation of MOS device affects the Trip Point shift in static type input buffer. We have performed the spice simulation and calculated the Trip Point with model parameter and measurement data so that how much the Trip Point(VLT) variate.

• Journal of KIISE:Software and Applications
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• v.26 no.3
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• pp.412-421
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• 1999

소프트웨어 개발 및 시스템을 구현하기 위해 사용되고 있는 대표적인 프로세스 모델이 IEEESTD1074-1991, ISO/IEC DIS12207-1, SPICE 모델, MIL-STD 498이다. 이들을 실제 국내 프로젝트들에 적용하기 위해 여러 가지 해결방안이 연구되고 있다. 일반적으로 프로젝트을 수행할 때, 개발 이전 단계 프로세스 설계의 실패는 전체 프로젝트 공정에 영향을 준다. 본 논문에서는 프로세스 중심 소프트웨어 엔지니어링 환경을 기반으로 하여 개발 이전 단계의 프로세스를 설계하는 방법을 제안한다. 이 방법은 프로세스, 활동, 테스크들의 연관관계를 도식화하고 있다. 그리고 설계된 결과를 국내 프로젝트들에 적용, 그 결과를 분석한다.

• Journal of Sensor Science and Technology
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• v.19 no.3
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• pp.191-196
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• 2010

In this paper, modeling of the non-ideal frequency response, especially "notch-and-spike" magnitude phenomenon and phase lag distortion, are discussed. To characterize the non-ideal frequency response, a new electro-mechanical simulation model based on SPICE is proposed using the driving loop of the capacitive vibratory gyroscope. The parasitic components of the driving loop are found to be the major factors of non-ideal frequency response, and it is verified with the measurement results.