• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 추계학술대회
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• pp.1892-1897
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• 2003

A new thermal inkjet printer head on SOI wafer with virtual valve was proposed. It was composed of two rectangular heaters with same size. So we could call it T-jet(Twin jet). T-jet has a lot of merits. It has the advantage of being fabricated with one wafer and is easy to change the size of chamber, nozzle, restrictor and so on. However, above all, It is the best point that T-jet has a virtual valve. And it was manufactured on SOI wafer. The chamber was formed in its upper silicon whose thickness was 40um. The chamber's bottom layer was silicon dioxide of SOI wafer and two heaters were located underneath the chamber's ceiling. And the restirctor was made beside the chamber. Nozzle was molded by process of Ni plating. Ni was 30um thick. Nozzle ejection test was performed by printer head having 56 nozzles in 2 columns with 600NPI(nozzle per inch) and black ink. It measured a drop velocity of 12m/s, a drop volume of 30pl, and a maximum firing frequency of 12KHz for single nozzle ejection. Throwing out the ink drop in whole nozzles at the same time, it was observed that the uniformity of the drop velocity and volume was less than 4%.

• Progress in Superconductivity
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• 제11권1호
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• pp.36-41
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• 2009

Superconducting quantum phenomena are getting attention from the field of metrology area. Following its first successful application of Josephson effect to voltage standard, piconewton force standard was suggested as a candidate for the next application of superconducting quantum effects in metrology. It is predicted that a micron-sized superconducting Nb ring in a strong magnetic field gradient generates a quantized force of the order of sub-piconewtons. In this work, we studied the design and fabrication of Nb superconducting quantum interference device (SQUID) on an ultra-thin silicon cantilever. The Nb SQUID and electrodes were structured on a silicon-on-insulator (SOI) wafer by dc magnetron sputtering and lift-off lithography. Using the resulting SOI wafer, we fabricated V-shaped and parallel-beam cantilevers, each with a $30-{\mu}m$-wide paddle; the length, width, and thickness of each cantilever arm were typically $440{\mu}m,\;4.5{\mu}m$, and $0.34{\mu}m$, respectively. However, the cantilevers underwent bending, a technical difficulty commonly encountered during the fabrication of electrical circuits on ultra-soft mechanical substrates. In order to circumvent this difficulty, we controlled the Ar pressure during Nb sputtering to minimize the intrinsic stress in the Nb film and studied the effect of residual stress on the resultant device.

• 한국재료학회지
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• 제16권5호
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• pp.308-311
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• 2006

The purpose of this study is to investigate the difference of the wafer nanotopography impact on the oxide-film thickness variation between the STI CMP using ceria slurry and STI CMP using fumed silica slurry. The nanotopography impact on the oxide-film thickness variation after STI CMP using ceria slurry is 2.8 times higher than that after STI CMP using fumed silica slurry. It is attributed that the STI CMP using ceria slurry follows non-Prestonian polishing behavior while that using fumed silica slurry follows Prestonian polishing behavior.

• 소성∙가공
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• 제13권3호
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• pp.285-289
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• 2004

Micro tensile test specimens of thin film single crystal silicon for the most useful structural materials in MEMS (Micro Electro Mechanical System) devices were fabricated using SOI (Silicon-on-Insulator) wafers and MEMS processes. Dimensions of micro tensile test specimens were thickness of $7\mu\textrm{m}$, width of 50~$350\mu\textrm{m}$, and length of 2mm. Top and bottom silicon were etched using by deep RIE (Reactive Ion Etching). Thin film aluminum markers on testing region of specimens with width of $5\mu\textrm{m}$, lengths of 30~$180\mu\textrm{m}$ and thickness of 200 nm for measuring tensile strain were fabricated by aluminum wet etching method. Fabricated side wall angles of aluminum marker were about $45^{\circ}~50^{\circ}$. He-Ne laser with wavelength of 633nm was used for checking fringed patterns.

• 반도체디스플레이기술학회지
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• 제7권1호
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• pp.1-5
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• 2008

In this paper, we fabricated pressure difference type gas flow sensor using only dry etching technology by ICP-RIE(inductive coupled plasma reactive ion etching). The sensor's structure consists of a common shear stress type piezoresistive pressure sensor with an orifice fabricated in the middle of the sensor diaphragm. Generally, structure like diaphragm is fabricated by wet etching technology using TMAH, but we fabricated diaphragm by only dry etching using ICP-RIE. To equalize the thickness of diaphragm we applied insulator($SiO_2$) layer of SOI(Si/$SiO_2$/Si-sub) wafer as delay layer of dry etching. Size of fabricated diaphragm is $1000{\times}1000{\times}7\;{\mu}m^3$ and overall chip $3000{\times}3000{\times}7\;{\mu}m^3$. We measured the variation of output voltage toward the change of gas pressure to analyze characteristics of the fabricated sensor. Sensitivity of fabricated sensor was relatively high as about 1.5mV/V kPa at 1kPa full-scale. Nonlinearity was below 0.5%F.S. Over-pressure range of the fabricated sensor is 100kPa or more.

• 센서학회지
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• 제19권1호
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• pp.31-35
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• 2010

High temperature micro pressure sensors were fabricated by using polycrystalline 3C-SiC piezoresistors grown on oxidized SOI substrates by APCVD. These have been made by bulk micromachining under $1{\times}1mm^2$ diaphragm and Si membrane thickness of $20{\mu}m$. The pressure sensitivity of implemented pressure sensors was 0.1 mV/$V{\cdot}bar$. The nonlinearity and the hysteresis of sensors were ${\pm}0.44%{\cdot}FS$ and $0.61%{\cdot}FS$. In the temperature range of $25^{\circ}C{\sim}400^{\circ}C$ with 5 bar FS, TCS (temperature coefficient of sensitivity), TCR (temperature coefficient of resistance), and TCGF (temperature coefficient of gauge factor) of the sensor were -1867 ppm/$^{\circ}C$, -792 ppm/$^{\circ}C$, and -1042 ppm/$^{\circ}C$, respectively.

• 대한기계학회논문집A
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• 제33권9호
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• pp.969-975
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• 2009

In this paper, bonded wafer analysis system is proposed using laser beam transmission; while the transmission model is derived by simulation. Since the failure of bonded wafer stems in void existence, transmittance deviations caused by the thickness of the void are analyzed and variations of the intensity through the void or defect easily have been recognized then the testing power has been increased. In addition, large screen display on laser study has been done which resulted in acquiring a feasible technique for analysis of the whole bonding surface. In this regard, three approaches are demonstrated in which Halogen lamp, IR lamp and laser have been tested and subsequently by results comparison the optimized technique using laser has been derived.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.355-355
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• 2010

We studied the dependence of the performance of schottky barrier metal-oxide-field effect transistors(SB MOSFETs) on the work function of source/drain metals. A strong impact of the various work functions and the light wavelengths on the transistor characteristics is found and explained using experimental data. We used an insulator of a high thickness (100nm) and back gate issues in SOI substrate, subthreshold swing was measured to 300~400[mV/dec] comparing with a ideal subthreshold swing of 60[mV/dec]. Excellent characteristics of Al/Si was demonstrated higher on/off current ratios of ${\sim}10^7$ than others. In addition, extensive photoresponse analysis has been performed using halogen and deuterium light sources(200<$\lambda$<2000nm).

• 센서학회지
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• 제22권5호
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• pp.369-373
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• 2013

In this paper, we developed contact type temperature sensor with single crystal silicon strip thermopile. This sensor consists of 15 p-type single crystal silicon strips, 17 n-types and contact electrodes on silicon dioxide silicon membrane. The result of electromotive force measuring showed very good characteristic as $15.18mV/^{\circ}C$ when temperature difference between the two ends of the thermopile occurs by applying thermal contact on the thermopile which was fabricated with silicon strip of $200{\mu}m$ length, $20{\mu}m$ width, $1{\mu}m$ thickness.

• 대한전자공학회논문지SD
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• 제43권4호
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• pp.23-30
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• 2006

본 연구에서는 나노 스케일 MuGFET(Mutiple-Gate FETs)의 단채널 효과와 corner effect를 3차원 시뮬레이션을 통하여 분석하였다. 문턱전압 모델을 이용하여 게이트 숫자(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4)를 구하였으며 추출된 게이트 숫자를 이용하여 각각의 소자 구조에 맞는 natural length($\lambda$)값을 얻을 수 있었다. Natural length를 통하여 MuGFET의 단채널 효과를 피할 수 있는 최적의 소자 구조(실리콘 두께, 게이트 산화막의 두께 등)를 제시 하였다. 이러한 corner effect를 억제하기 위해서는 채널 불순물의 농도를 낮게 하고, 게이트 산화막의 두께를 얇게 하며, 코너 부분을 약 17%이상 라운딩을 해야 한다는 것을 알 수 있었다.