• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 하계학술대회 논문집
• /
• pp.874-877
• /
• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• 한국전기전자재료학회논문지
• /
• 제16권4호
• /
• pp.292-297
• /
• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 하계학술대회 논문집
• /
• pp.95-96
• /
• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• 대한금속재료학회지
• /
• 제46권1호
• /
• pp.39-43
• /
• 2008

PSII (Plasma Source Ion Implantation) using high density pulsed ICP source was employed to implant oxygen ions in Si wafer. The PSII technique can achieve a nominal oxygen dose of $3 {\times}10^{17}atoms/cm^2$ in implantation time of about 20min. In order to prevent oxidation of SOI layer during high temperature annealing, the wafer was capped with $2,000{\AA}$ $Si_3N_4 $ by PECVD. Cross-sectional TEM showed that continuous $500{\AA}$ thick buried oxide layer was formed with $300{\AA}$ thick top silicon layer in the sample. This study showed the possibility of SOI fabrication using the plasma source ion implantation with pulsed ICP source.

• 한국세라믹학회지
• /
• 제36권8호
• /
• pp.863-870
• /
• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

• 한국전기전자재료학회논문지
• /
• 제16권5호
• /
• pp.365-371
• /
• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• 대한전자공학회논문지SD
• /
• 제41권10호
• /
• pp.51-56
• /
• 2004

광소자의 재료물질로서 특성이 우수하며 열광학계수가 큰 silicon을 기반으로 한 SOI (Silicon-on-insulator)를 사용하여 열광학 1×2 광스위치를 제안, 제작하였다. SOI wafer는 도파로가 형성될 상위 Si 층(n=3.5)과 클래딩 영역이 될 산화막 매립층(n=1.5) 그리고 기판인 Si인 3층으로 이루어진다. BPM(Beam propagation method) 전산모의를 통해 20dB 이상의 누화특성을 갖는 단일모드의 1×2 비대칭 y-분기 광도파로를 형성하고, 열확산 전산모의를 통해 금속열선을 설계 제작하였다. 제작된 광스위치는 약 3.5 watts의 구동 전력에서 20dB 이상의 채널간 누화가 측정되었다.

• 한국표면공학회지
• /
• 제29권5호
• /
• pp.482-486
• /
• 1996

The progress of microelectronics technology has been requiring agressive developments of device technologies. Also the requirements of the next generation devices is heading to the limits of their functions and materials, and hence asking the very specific silicon wafer such as SOI(Silicon On Insulator) wafer. The talk covers the dome stic and world-wide status of SOI device developments and applications. The presentation will also touch some predictions such as SOI device prgress schedules, impacts on the normal wafer developments, market sizes, SOI wafer prices, and so on. Finally it will cover technical aspects which are silicon oxide conditions for bonding, point defects and, surface contaminations. These points will be hopefully overcome by involved people in microelectronics industry.

• 한국마린엔지니어링학회:학술대회논문집
• /
• 한국마린엔지니어링학회 2000년도 춘계학술대회 논문집(Proceeding of the KOSME 2000 Spring Annual Meeting)
• /
• pp.105-109
• /
• 2000

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor the size of the pressure sensor diaphragm have become smaller year by year and a microaccelerometer with a size less than 200-300${\mu}m$ has been realized. In this paper we study some of the micromachining processes of SOI(silicon on insulator)for the microaccelerometer and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in structural engineering discipline for design of SOI wafers. Successful thermal behaviors analysis and design of the SOI wafers based on the tunneling current concept using SOI wafer depend on the knowledge abut normal mechanical properties of the SCS(single crystal silicon)layer and their control through manufacturing process

• 센서학회지
• /
• 제1권2호
• /
• pp.131-145
• /
• 1992

본 논문은 SOI트랜스듀서 및 회로를 위해, Si 직접접합과 M-C국부연마법에 의한 박막SOI구조의 형성 공정을 기술한다. 또한, 이러한 박막SOI의 전기적 및 압저항효과 특성들을 SOI MOSFET와 cantilever빔으로 각각 조사했으며, bulk Si에 상당한다는 것이 확인되었다. 한편, SOI구조를 이용한 두 종류의 압력트랜스듀서를 제작 및 평가했다. SOI구조의 절연층을 압저항의 유전체분리층으로 이용한 압력트랜스듀서의 경우, $-20^{\circ}C$에서 $350^{\circ}C$의 온도범위에 있어서 감도 및 offset전압의 변화는 자각 -0.2% 및 +0.15%이하였다. 한편, 절연층을 etch-stop막으로 이용한 압력트랜스듀서에 있어서의 감도변화를 ${\pm}2.3%$의 표준편차 이내로 제어할 수 있다. 이러한 결과들로부터 개발된 SDB공정으로 제작된 SOI구조는 집적화마이크로트랜스듀서 및 회로개발에 많은 장점을 제공할 것이다.