• Title/Summary/Keyword: SDH network

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Performance Analysis of Synchronization Clock with Various Clock States Using Measured Clock Noises in NG-SDH Networks (NG-SDH망에서 측정된 클럭잡음을 이용한 다양한 클럭상태에 따른 동기클럭 성능분석)

  • Lee, Chang-Ki
    • The KIPS Transactions:PartC
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    • v.16C no.5
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    • pp.637-644
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    • 2009
  • A study about performance analysis of synchronization clock using measured clock noises is required. Therefore this paper executed the study for performance analysis of synchronization clock and acquirement of maximum number of network node with various clock states using measured clock noises in NG-SDH networks. Also this paper generated a suitable clock model using measured clock noises, and carried out simulations with various clock states. Through the simulation results, maximum numbers were 80 or more network nodes in normal state, and were below 37 nodes in short-term phase transient(SPT) state, and were 50 or more in long-term phase transient(LPT) state. Accordingly this study showed that maximum numbers to meet ITU-T specification were below 37 network nodes in three clock states. Also this study showed that when SPT or LPT states occur from NE network before DOTS system, synchronization source must change with other stable synchronization source of normal state.

A Performance Analysis on Steady-state Synchronous Clock in NG-SDH Network (광전송망에서 정상상태 동기클럭 성능)

  • Yang, Choong-Reol;Ko, Je-Soo;Lee, Chang-Ki;Kim, Whan-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.6B
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    • pp.305-315
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    • 2007
  • In this paper, We generated a wander generation model from really measured clock noise data on the transmission node and DOTS in NG-SDH network. and then, We presented the performance of Synch. clock and maximum node level capable network configuration through the clock characteristics simulation on network having the steady-state clock.

A study on the minimizing the number of lightpath in SDH/WDM mesh networks (SDH/WDM Mesh 망 설계 기법에 관한 연구)

  • 김지호;정지복;이희상;정성진
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 2000.04a
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    • pp.216-219
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    • 2000
  • 본 연구는 WDM Mesh 망에서 SDH 수요가 주어졌을 때, 여러 개의 SDH 수요를 효과적으로 routing하는 방법을 통해 grooming 효과를 극대화시켜 전체 Mesh망에서 사용되어지는 총 Lightpath의 수를 줄이는 것을 목적으로 한다. 그리고 이렇게 해서 구해진 Lightpath의 수를 각 링크의 용량제약으로 하여 SDH 수요의 routing 비용을 최소화하는 것을 부차적인 목적으로 한다. 이것을 수리모형으로 바꾸면, Network Synthesis 문제와 Integer Multicommodity 문제로 모형화 할 수 있다. 해법으로는 Path-Formulation을 통한 분지평가법을 사용하였다. 전산실험결과를 보면 상용 패키지인 CPLEX를 이용하여 푼 것에 비해 수행속도 면에서 훨씬 빠르게 나타났고, 문제의 사이즈가 커짐에 따라 CPLEX를 사용하여 해결할 수 없는 문제에 대해서도 해를 구할 수 있었다.

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FPGA Implementation of a Pointer Interpreter for SDH/SONET Network Synchronization (SDH와 SONET망의 동기화를 위한 포인터 해석기의 FPGA 구현)

  • 이상훈;박남천;신위재
    • Journal of the Institute of Convergence Signal Processing
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    • v.5 no.3
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    • pp.230-235
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    • 2004
  • This paper describes FPGA implementation of a pointer interpreter which can support a synchronization of SDH(or SONET)-based transmission network. The pointer interpreter consists of a pointer-word extractor and a pointer-word interpreter The pointer-word extractor which is composed of mod-6480 counter, shift register and pointer synchronizing block, finds out the H1 and H2 pointer word from a 51.84 Mb/s AU-3/STS-1 data frame and then performs the synchronizing with a 6.48 Mb/s by dividing them in 8. Based on the extracted pointer word, pointer-word interpreter analyzes pointer states such LOP, AIS and NORM according to pointer state-transition algorithm. It consists of a majority vote, a pointer word valid/invalid check, a pointer justification, and a pointer state check. The simulation results of Xilinx Virtex XCV200PQ240 FPGA chip shows the exact pointer word extraction and correct decision of pointer status based on extracted pointer word. The proposed pointer interpreter is suitable for pointer interpretation of 155 Mb/s STM-1/STS-3 frame.

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Study of An All-Optical WDM Transport Network of a Multiple Self-Healing Ring Architecture in SDH Based (SDH기반 Multiple Self-Healing Ring 구조의 전광 전달망 구성방안 및 성능분석)

  • 안기석;정노선;홍상기;홍종일;강철신
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.17-20
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    • 1999
  • In these days, wavelength division multiplexing(WDM) all-optical network are being deployed to support various multimedia communication services. In this paper, various WDM all-optical network are discussed, and a design of an all-optical backbone network has been proposed by using multiple self-healing ring technology. The proposed multiple self-healing ring network improves network expandability and efficiency of bandwidth, while it retains simplicity and ease of network control, which are from the nature self-healing ring. Using PDI traffic modeling technique, a well-balanced all-optical backbone network using multiple self-healing ring is designed for the 2010s in Korea.

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Short-term Stable Characteristic Analysis of the Synchronized Clock in the Synchronization Network and SDH Based Network (동기망과 동기식 전송망에서의 동기클럭 단기안정 특성 분석)

  • Lee, Chang-Gi
    • The KIPS Transactions:PartC
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    • v.8C no.3
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    • pp.299-310
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    • 2001
  • 동기망과 동기식 전송망을 설계할 때에는 동기클럭의 단기안정 클럭특성과 이에 따른 망구성 노드수가 중요하게 고려되어야 할 사항이다. 또한 동기망과 전송망을 동시에 고려하여야 한다. 만일 전송망 만을 고려한다면 동기망에서의 발생할 수 있는 클럭성능 저하를 반영시킬 수 없기 때문이다. 지금까지의 연구는 주로 동기식 전송망만을 적용하여 연구되었다. 본 논문에서는 동기망과 동기식 전송망을 통합 고려하고, 최악의 원더생성을 적용하였을 때의 세가지 클럭상태에 따른 망동기클럭의 MTIE와 TDEV 특성을 얻었다. 또한 현 ITU-T 규격을 적용하여 세 가지 클럭상태에 따른 최대 망 구성 노드수를 구하였다.

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A Path Control Switch Chip for an Unidirectional Path Swithced Ring (단방향 경로 스위칭 링을 위한 경로 제어 스위치 소자)

  • 이상훈
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.8A
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    • pp.1245-1251
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    • 1999
  • A 1.25Gb/s path control switch chip has been designed and implemented with COMPASS tool and 0.8${\mu}{\textrm}{m}$ CMOS gate-array of LG semiconductor. This device controls the path of digital singnals in SDH-based transmission system. The proposed switch chip is suitable for self-healing operations both in a linear network and an unidirectonal ring, The self-healing operation of the switch is effectively done by the configuration information stored in the resisters of the switch. The test device adapted to SDH-based transmission system, show immediate restoration and a 10-11~10-12 bit error raito. And 2.5Gb/s or more high throughput can be realized by combining rwo identical or more switches with the parallel architecture.

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Development of Simulator for Performance Analysis of Synchronization Clock in the Synchronization Network and Transmission Network (동기망과 전송망에서의 동기클럭 성능 분석을 위한 시뮬레이터 개발)

  • Lee, Chang-Ki
    • The KIPS Transactions:PartC
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    • v.11C no.1
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    • pp.123-134
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    • 2004
  • The synchronized clock performance in the synchronization network and SDH transmission network design is an important element in aspect of guaranteeing network stability and data transmission. Consequently the simulator which can applicable various parameters and several input levels from the best state to the worst state for performance analysis of the synchronized clock is required in case of network design. Therefore, in this paper, 1 developed the SNCA and TNCA for analysis of the synchronized clock in the synchronization network and transmission network. And utilizing these simulators with various wander generation, node number and clock state, 1 obtained the synchronized clock characteristics and maximum network nodes In NE1, NE2 and NE3 transmission network and DOTS1, DOTS2 synchronization network.

A Study on the Protection of EPON (EPON 장애 대책에 관한 연구)

  • Koo Bon-Jeong;Hur Jeong;Kim Sunghwi;Cho Seong-Dae;Park Youngil
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.11A
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    • pp.1231-1236
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    • 2004
  • Network protection has been mainly applied to trunk network. PTP, ring, linear, mesh topologies of SONET/SDH system and 565 Mbps PDH systems are among those examples. But, as larger capacity PON system is introduced, protection in access network system also becomes necessary. In this paper, an efficient EPON protection scheme utilizing the EPON's frame and protocol is proposed and the implementation results showing protection within 1 msec are provided.