• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.3
• /
• pp.398-402
• /
• 2008

Recently, the development of superconducting fault current limiters (SFCLs) has been required as power demands increase in the power system. A distribution-level prototype resistive SFCL using coated conductor (CC) has been developed by Hyundai Heavy Industries Co., Ltd. and Yonsei University for the first time in the world. The ratings of the SFCL are 13.2kV/630A at normal operating condition. A novel non-inductive winding method is used in fabricating coils so there is almost zero impedance during normal operation. The distribution SFCL is cooled by sub-cooled liquid nitrogen $(LN_2)$ of 65K and 3 bar to enhance cryo-dielectric performance, critical current density, and thermal conductivity. In order to make reliable operation of an SFCL in real power systems, we monitored and controled its operation conditions by using supervisory control and data acquisition (SCADA) method. Thus, a monitoring system for the SFCL employing information technology (IT) is proposed and developed to be on the lookout for the operation conditions such as inside temperature, inside pressure, $LN_2$ level, voltage and current. Since operation temperature should be kept constant, bang-bang control for temperature feedback with a heater attached to the cold head of cryo-cooler is applied to the system. Short-circuit tests with prospective fault current of 10kA and AC dielectric withstand voltage tests up to 143kV for 1 minute were successfully performed at Korea Electrotechnology Research Institute. This paper deals with the development of a distribution level SFCL and its monitoring system for reliable operation.

• Journal of IKEEE
• /
• v.23 no.3
• /
• pp.917-924
• /
• 2019

This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.12
• /
• pp.90-95
• /
• 2014

This paper presents a VHF/UHF-band variable gain low noise amplifier for multi-standard mobile TV tuners. A proposed VHF-band variable gain amplifier is composed of a resistive shunt-feedback low noise amplifier to remove external matching components, a single-to-differential amplifier with input PMOS transcoductors to improve low frequency noise performance, a variable shunt-feedback resistor and an attenuator to control variable gain range. A proposed UHF-band variable gain amplifier consists of a narrowband low noise amplifier with capacitive tuning to improve noise performance and interference rejection performance, a single-to-differential with gm gain control and an attenuator to adjust gain control range. The proposed VHF-band and UHF-band variable gain amplifier were designed in a $0.18{\mu}m$ RF CMOS technology and draws 22 mA and 17 mA from a 1.8 V supply voltage, respectively. The designed VHF-band and UHF-band variable gain amplifier show a voltage gain of 27 dB and 27 dB, a noise figure of 1.6-1.7 dB and 1.3-1.7 dB, OIP3 of 13.5 dBm and 16 dBm, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.8
• /
• pp.22-26
• /
• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.9
• /
• pp.31-39
• /
• 2011

In this paper, we propose a signal readout system with small area and low power consumption for CNT sensor arrays. The proposed system consists of signal readout circuitry, a digital controller, and UART I/O. The key components of the signal readout circuitry are 64 transimpedance amplifiers (TIA) and SAR-ADC with 11-bit resolution. The TIA adopts an active input current mirror (AICM) for voltage biasing and current amplification of a sensor. The proposed architecture can reduce area and power without sampling rate degradation because the 64 TIAs share a variable gain amplifier (VGA) which needs large area and high power due to resistive feedback. In addition, the SAR-ADC is designed for low power with modified algorithm where the operation of the lower bits can be skipped according to an input voltage level. The operation of ADC is controlled by a digital controller based on UART protocol. The data of ADC can be monitored on a computer terminal. The signal readout circuitry was designed with 0.13${\mu}m$ CMOS technology. It occupies the area of 0.173 $mm^2$ and consumes 77.06${\mu}W$ at the conversion rate of 640 samples/s. According to measurement, the linearity error is under 5.3% in the input sensing current range of 10nA - 10${\mu}A$. The UART I/O and the digital controller were designed with 0.18${\mu}m$ CMOS technology and their area is 0.251 $mm^2$.