• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1187-1190
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• 2005

The ramp reset driving method proposed in [1] has been widely adopted because of its stability and high contrast ratio. However, when the conventional ramp reset method is used in PDPs of higher resolution, the long required time for reset often becomes a problem. In this paper, a new driving method that requires much less reset time and that significantly improves the contrast ratio is introduced. Using this new driving method, the required time for reset could be reduced to 150us from 350us of the conventional ramp reset method, and the contrast ratio is almost infinite because the luminance of the off-cell is almost zero.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.199-202
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• 2002

In general, the background light produced during the reset period deteriorates the dark room contrast ratio in AC PDP. In this paper, we propose a modified ramp reset pulse that can reduce the background light to imperceptible level. In the new reset waveform, the discharges between the scan and sustain electrodes are minimized by applying a positive bias voltage to the sustain electrode and only the weak discharges between the scan and address electrodes occur during the reset period. We adopted a MgO coated phosphor layer to get the same level of voltage margin in the new reset pulse scheme compared to that of the conventional ramp reset pulse one. As a result, the voltage margin is maintained at the same level and the dark room contrast ratio is improved dramatically.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.12
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• pp.1004-1008
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• 2012

The effect of address discharge characteristics by selective reset method is investigated to prevent the weakness of address discharge in the middle of a TV-field without increase of the black luminance. To reduce black luminance in AC PDP usually, the first subfield during one TV frame adopted the conventional rising ramp-reset waveform, whereas the other subfields adopted the subsidiary reset waveform without rising ramp type. As the wall charge for the address discharge was accumulated by only the rising ramp waveform during the first reset period, the wall charge on three electrodes was disappeared as time passed and the address discharge would be weakened in the rear subfields. To prevent a reduction of the address discharge characteristics without decrease the black luminance, the modified rising ramp reset waveform was adopted only in the sixth subfield. As a result, a modified driving method could improve the address discharge characteristics compared with selective reset driving scheme with almost the same black luminance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.83-88
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• 2003

The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with $492(H){\;}{\times}{\;}510(V)$ pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.2
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• pp.93-101
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• 2003

Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. The scan design cannot be used in a design with scan design rule violations without modifying the design. The most important scan design rule is concerning clock and reset signals to pins of the flip-flops or scan cells. Clock and Reset pins of every scan cell must be controllable from top-level ports. We propose a new technique to re-design gated clocks and resets which violate the scan design rule concerning the clock and reset pins. This technique substitutes synchronous sequential circuits for gated clock and reset designs, which removes the clock and reset rule violations and improves fault coverage of the design. The fault coverage is improved from $90.48\%$ to $100.00\%$, from $92.31\%$ to $100.00\%$, from $95.45\%$ to $100.00\%$, from $97.50\%$ to $100.00\%$ in a design with gated clocks and resets.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.722-725
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• 2013

In this work, we have been analyzed the characteristics of ReRAM with different annealing condition and temperature. The ReRAM devices with top electrode=150nm, bottom electrode=150nm, oxide thickness=70nm and annealing temperature=$500^{\circ}C$, $850^{\circ}C$ have been used in characterization. The Set/Reset voltage, sensing window and resistivity have been characterized. From the measurement results, the Set/Reset voltage and sensing window have been enhanced as the annealing temperature has been increased. But it has been decreased as the temperature performance has been increased. In case of the annealing temperature=$850^{\circ}C$, the variation of Set/Reset voltage was lower than that of other condition. But the variation of sensing window was the lowest when the annealing temperature was $500^{\circ}C$. With considering the variation of Set/Reset voltage and sensing window, the devices annealed at $850^{\circ}C$ showed the best performance to ReRAM.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.10
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• pp.517-521
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• 2001

The voltage controlled ramp(VCR) waveform has recently been introduced in the reset period prior to addressing for plasma display. However, this method shows the oscillation of gap voltage when the ramp rate is increased in order to reduce reset period. In this paper a current controlled ramp(CCR) waveform method is suggested. This method can suppress the oscillation of gap voltge under the condition of shorter ramp time. Moreover, the reset time can be reduced about 30% compared with VCR method under the same background luminance.

• Phonetics and Speech Sciences
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• v.2 no.1
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• pp.33-39
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• 2010

This study investigates the effect of pitch range reset in Korean listeners' processing of syntactically ambiguous participle structures. Unlike Japanese and English,in Korean, the downtrend or the reset of pitch range does not consistently differentiate Accentual Phrases (AP), a lower level of phrasing, from Intonational Phrases (IP), a higher level of phrasing. Therefore, we explore Korean listeners' comprehension patterns for syntactically ambiguous speech strings varying in 1) the relative height of F0 peaks across prosodic units, and 2) the types of prosodic phrasing, to see whether pitch range reset informs the recovery of syntactic structure even though it is not reflected in the intonational hierarchy in Korean. The results show that the hierarchical level of prosodic phrasing affects the parsing pattern of syntactic ambiguity. The pitch range reset also cued the location of syntactic boundaries, but this effect was confined to phrases across AP.

• Journal of Information Display
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• v.2 no.4
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• pp.39-45
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• 2001

The voltage controlled ramp(VCR) waveform has recently been introduced in the reset period prior to addressing for plasma display. However, this method results in the oscillation of the gap voltage when the ramp rate is increased so as to reduce reset period. In this paper a current controlled ramp(CCR) waveform method in the reset period is suggested. This method can suppress the oscillation of gap voltage under the condition of shorter ramp time. Moreover, the reset time can be reduced by about 30 % compared with the VCR method under the same background luminance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04a
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• pp.159-161
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• 2000

After the square type reset pulse, the condition of remaining wall charge has been experimentally investigated in AC-PDP with VDS (Versatile Driving Simulator) system, in which arbitrary driving waveform and sequence can be used. After the self-discharge process, almost wall charges are eliminated. But some wall charges are not and its quantity is dependent on the voltage of the reset pulse. When the voltage of the reset pulse is growing, its quantity is decreased. But if the voltage of the reset pulse is above 300V, the wall voltage due to remaining wall charge is constant and its value is found out 6V. Also it is found that its polarity is always same with the one made by the reset pulse. It means that the polarity is not changed by the self-discharge.