• Journal of Information Display
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• 제10권2호
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• pp.54-61
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• 2009

The results of the optimization of the organic passivation process for fabricating thin-film transistors (TFTs) with a high aperture ratio on a seventh-generation glass (2200${\times}$1870 mm) substrate for LCD-TV panels are reported herein. The optimization of the organic passivation process has been verified by checking various factors, including the material properties (e.g., thickness, stain, etching, thermal reflow) and the effects on the TFT operation (e.g., gate/data line delay and display-driving properties). The two main factors influencing the organic passivation process are the optimization of the final thickness of the organic passivation layer, and the gate electrode. In conclusion, the minimum possible final thickness was found to be $2.42{\um}m$ via simulation and pilot testing, using the full-factorial design. The optimization of the organic passivation layer was accomplished by improving its brightness by over 10 cd/$m^2$ (ca. 2% luminance) compared to that of the conventional organic passivation process. The results of this research also help reduce the reddish stain on display panels.

• ETRI Journal
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• 제35권2호
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• pp.340-343
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• 2013

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of $130{\mu}m$ is successfully formed.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2007년 추계학술발표대회 개요집
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• pp.232-234
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• 2007

This study conducts numerical simulations of Isotropic conductive adhesives using low melting point alloy fillers during the reflow process. The CIP method and predictor-corrector method are used to simulate more accurately on free surface flow of low melting point alloy fillers. For finding out optical conditions to obtain reliable conduction paths, the present study conducts extensive numerical simulations.

• 대한금속재료학회지
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• 제48권6호
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• pp.557-564
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• 2010

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.59-63
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• 2013

In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.65-68
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• 2013

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process. A selective solder bumping mechanism without the mask is based on the material design of SBM. Maskless screen printing process can implement easily a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology. Its another advantage is ternary or quaternary lead-free SoP can be formed easily. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 ${\mu}m$ is, successfully, formed.

• ETRI Journal
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• 제34권5호
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• pp.706-712
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• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

• 대한기계학회논문집A
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• 제28권6호
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• pp.709-716
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• 2004

In order to prevent the interface delamination of an plastic IC package in the infrared (IR) soldering process, we tried to reduce stress by parameterization, sensitivity analysis and unconstraint optimization. The design variables of dimensions and material properties are determined among all the possible variables from the parametric study. Their optimized values are determined by applying the unconstraint optimization to the parameterized IC package. The maximum von-Mises stress value decreases greatly by optimum design.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권8호
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• pp.414-418
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• 2001

Failure modes of Mo-tip FEA were investigated in detail as a preliminary study for the application of Mo-tip FEA to the CRT electron-gun as a cold cathode. It was identified that the destruction of Mo-tip FEA was originated from reflowing of arc-current during the spot-knocking process followed by secondary arc between gate electrode and cathode substrate. In order to prevent Mo-tip FEA from destruction due to arc-current, two kinds of methods were suggested, that is one is to provide the by-pass of the reflow current and the other is to install a current limiter in the path of gate connection line.

• Journal of Welding and Joining
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• 제13권4호
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• pp.14-23
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• 1995

Micro soldering 기술의 응용은 주로 전자제품에 이용되며, 특히 컴퓨터 정보 통신 기기의 집합.접속 기술의 중추적인 역할을 하고 있다. 아울러 이 분야는 일본, 미국이 선구적인 역할을 하고 있으며, 예를 들어 일본 전자산업의 1994년도 생산액이 앤 고의 열쇠에 불구하고 민생용.산업용 전자기기 및 전자 부품의 3부분에서 약 .yen.30조(250조원)에 달한 것으로 보면 그 규모 및 중요성을 알 수 있다. 이것은 기본 적으로 반도체의 집적도가 높아진것(LSI.rarw.VLSI.rarw.ULSI)과 아울러 소자를 접합 접속시키는 기술이 확보되었기 때문에 이루어진 결과라고 말할 수 있다. 따라서 본 기술 해설에서는 접합.접속 기술의 하나인 Micro soldering의 각종 프로세스 중에서 도 특히 기본이 되는 리플로우 프로세스(reflow process)를 중심으로 기술하였으며 아울러 신뢰성의 제반사항에 관하여 간략하게 기술하였다.