• Title/Summary/Keyword: Reed-Solomon Code

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A Study on the Performance Improvement of DM-SS Watermarking with RS code in OFDM/QPSK Wireless channel Environment (OFDM/QPSK 무선 채널 환경에서 RS 부호화 기법을 적용한 DM-SS 워터마킹 성능 개선에 관한 연구)

  • Jo Song-Back;Kim Ji-Woong;Kang Heau-Jo
    • Journal of Digital Contents Society
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    • v.5 no.4
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    • pp.316-320
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    • 2004
  • In this paper, we propose OFDM/QPSK technique for copyright protection of image data to insert watermark. And, we improve performance of restoration watermark by Reed-Solomon coding that robust burst error. In here, we consider several factors about external effect of image over OFDM/QPSK transmission system.

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The Performance evaluation of the Reed-Solomon Product Codes in Burst Error (Burst Error Channel에서 Reed-Solomon Product 코드의 에러 정정 평가 방법)

  • Han, Sung-Hyu;Lee, Yoon-Woo;Hwang, Sung-Hee;Ryu, Sang-Hyun;Shin, Dong-Ho;Joong-Eor, Joong-Eor
    • Proceedings of the KIEE Conference
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    • 2001.07d
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    • pp.2493-2495
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    • 2001
  • Burst Error Channel의 에러 정정 기술로써 Reed-Solomon Product Code(RSPC)가 광범위하게 사용되고 있다. 그러나 Random Error Channel과는 달리 Burst Error Channel 상에서 RSPC의 에러 정정 평가 방법에는 많은 어려움이 있다. 우리는 이번 논문에서 Burst Error Channel 상에서 RSPC의 Error Correction Capability의 확률적인 계산 방법을 기술하려 한다.

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Complexity Analysis of a VHDL Implementation of the Bit-Serial Reed-Solomon Encoder (VHDL로 구현된 직렬승산 리드솔로몬 부호화기의 복잡도 분석)

  • Back Seung hun;Song Iick ho;Bae Jin soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.3C
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    • pp.64-68
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    • 2005
  • Reed-Solomon code is one of the most versatile channel codes. The encoder can be implemented with two famous structures: ordinary and bit-serial. The ordinary encoder is generally known to be complex and fast, while the bit-serial encoder is simple and not so fast. However, it may not be true for a longer codeword length at least in VHDL implementation. In this letter, it is shown that, when the encoder is implemented with VHDL, the number of logic gates of the bit-serial encoder might be larger than that of the ordinary encoder if the dual basis conversion table has to be used. It is also shown that the encoding speeds of the two VHDL implemented encoders are exactly same.

Erasure decoding strategies for RS product code reducing undetected error rate (검출 불능 오류율을 향상기키는 Reed-Solomon 적부호의 이레이져 복호방법)

  • 김정헌;염창열;송홍엽;강구호;김순태;백세현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.4B
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    • pp.427-436
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    • 2001
  • RS product codes are widely used in digital storage systems. There are lots of decoding strategies for product code for short-length RS codes. Unfortunately many of them cannot be applied to long-length RS product codes because of the complexity of decoder. This paper proposes new decoding strategies which can be used in long length RS product codes.

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High-Performance Variable-Length Reed-Solomon Decoder Architecture for Gigabit WPAN Applications (기가비트 WPAN용 고성능 가변길이 리드-솔로몬 복호기 구조)

  • Choi, Chang-Seok;Lee, Han-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.1
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    • pp.25-34
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    • 2012
  • This paper presents a universal architecture for variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS(255,239) code but various shortened RS codes. Moreover, variable-length architecture provides variable low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-$nm$ CMOS standard cell technology, the proposed RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-$Gbps$ data rate at clock frequency 300 $MHz$.

Design of Adaptive Reed-Solomon Encoder for Multi QoS Services or Time-Varying Channels (다중 QoS 서비스와 시변 채널을 위한 적응형 RS 부호기의 설계)

  • 공민한;송문규;김응배;정찬복
    • Proceedings of the IEEK Conference
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    • 2001.06a
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    • pp.113-116
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    • 2001
  • Reed-Solomon(RS) code is the most powerful burst error correcting code. In Ois paper, the architecture for the adaptive RS encoder adaptable for multi QoS requirements or time-varying channel environments has been designed. In the adaptive RS code, the message length k and the error correction capability t are allowed to be variable so that the block length n is also variable. We proposed the architecture of the adaptive RS encoder by designing the optimal structure of Galois fields multiplier with comparison of fixed multiplier and variable multiplier. The proposed architecture is implemented in VHDL and verified with the simulation tool

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A Study on Decoding Method of the R-S Code for Double-Encoding System in the Frequency Domain (주파수 영역에서 2중부호화 R-S부호의 부호방식에 관한 연구)

  • 전경일;김남욱;김용득
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.14 no.3
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    • pp.216-226
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    • 1989
  • In this paper, we explain about an outline of the decoding method for double encoding system using the error correcting capacitance and a simple decoding method. We have been taken formation two-dimension code word of doubly-encoded code using $C_1$(32, 28, 5) and $C_2$(32, 26, 7) Reed-Solomon codes, and had computer simulation of the erroe correcting processes in frequency domain. On these processes, the newly developed digital signal processing technology such as error correction using Berlekamp-Massey algorithm in frequency domain have been proven.

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Three-Parallel Reed-Solomon based Forward Error Correction Architecture for 100Gb/s Optical Communications (100Gb/s급 광통신시스템을 위한 3-병렬 Reed-Solomon 기반 FEC 구조 설계)

  • Choi, Chang-Seok;Lee, Han-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.48-55
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    • 2009
  • This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-${\mu}m$ CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-${\mu}m$ CMOS technology. As a result, the proposed three-parallel RS-FEC architecture has a much higher data processing rate and low hardware complexity compared with the conventional two-parallel, three-parallel and serial RS-FEC architectures.

Block Error Performance improvement of the DS/CDMA BPSK system with MRC Diversity and Channel coding Techniques in Nakagami Fading Channel. (Nakagami 페이딩 채널에서 MRC 다이버시티와 채널 부호화 기법을 사용한 DS/CDMA BPSK 시스템의 블록 오율 성능 개선)

  • 강희조;노재성;조성준
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.3A
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    • pp.391-398
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    • 2000
  • In this paper, MRC(Maximum Ratio Combine) diversity, (23, 12) Golay code, (7, 5) Reed-Solomon code, and (3, 1) majority selection code are employed to improve the performance of DS/CDMA BRSK in Nakagami fading channel. and MRC diversity combined with other coding techniques is suggested, with which, the performance of DS/CDMA BRSK is compared and analyzed. Also, system required Eb/N0 to meet BER=10-5 for multi user data communication is obtained according to each techniques. From the results, when each techniques is employed to DS/CDMA BRSK system. coding employed system shows better performance than diversity employed system. Especially, Golay code shows better performance than oter codes. also MRC diversity is employed, the number of multiple access user to meet data communication requirement of BER=10-5 can accomodate up to 8 users. and when each code is employed, Golay code, majority selection code, and Reed-Solomon code shows the capacity of 14, 12, and 10 user respectively. But MRC diversity combined with coding techniques can reduce restriction of multiple access user. However, it is desirable these combined technique are employed according to service types and requirements provided.

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Efficient secret sharing scheme with cheater identification based on QR code

  • Huang, Peng-Cheng;Chang, Chin-Chen;Li, Yung-Hui;Liu, Yanjun
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.13 no.10
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    • pp.5144-5160
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    • 2019
  • Secret sharing is an effective way of protecting secret messages. However, the traditional secret sharing schemes are considered meaningless due to malicious people attention which might raise risks. To overcome the weakness, this paper presents an effective secret sharing scheme with the functionality of cheater identification, based on meaningful QR code. The secret message will be split and concealed in the padding region of cover QR codes with the assistance of Latin square and it can be completely restored when all the involved participants cooperate. The concealing strategy exploits the characteristic of Reed-Solomon (RS) code to ensure the strong robustness of generated QR code pseudo-shares. The meaningful QR code pseudo-shares help to reduce the curious of unrelated persons. Some experiments were done to evaluate the performance of proposed scheme. The results showed that the proposed scheme is feasible, efficient and secure compared to the other existing schemes. It also achieves a higher secret payload and maintains stronger robustness.