• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.706-710
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• 1988

Using back electro-motive force(EMF) signals of a brushless DC motor, the sensorless micro-processor controlled drive system was developed. In this new commutation method, the manual pulses are used for relatively short accelerating phase and then the exact commutational positions are detected based upon the back emf signals. The hardware and software implementations with the experiment to compare the performance of the developed system with the, conventional system using hall effect sensors are included. By reducing the number of the required sensors in the artificial heart control system, the total reliability will be incresed.

• IEMEK Journal of Embedded Systems and Applications
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• 제15권5호
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• pp.235-242
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• 2020

This paper analyzes the effect of reduced output width of the truncated logarithmic multiplication and application to inferences using convolutional neural networks (CNNs). For small hardware overhead, output width is reduced in the truncated Mitchell multiplier, so that fractional bits in multiplication output are minimized in error-resilient applications. This analysis shows that when reducing output width in the truncated Mitchell multiplier, even though worst-case relative error increases, average relative error can be kept small. When adopting 8 fractional bits in multiplication output in the evaluations, there is no significant performance degradation in target CNNs compared to existing exact and original Mitchell multipliers.

• Proceedings of the IEEK Conference
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.397-400
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• 1999

As the result of enhancement of CAD, Design Automation and manufacturing technology, it's on the increasing complexity, integration ratio, data signals, and pin count to IC chips. This brings about difficulties of testing, and incresing test time. Now One of the most cost-consuming procedure as integration ratio increases is the testing step. In this paper, we propose a new method, “Efficient TP(test point) assignment algorithm” using “input grouping”, This is helpful method to reducing test length without losing fault coverage. Experimental results show that proposed method reduces test length remarkably and doesn't miss fault coverage, with low hardware overhead Increasing.

• Journal of Korea Society of Digital Industry and Information Management
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• 제8권1호
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• pp.107-115
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• 2012

This paper proposes on the structure for reducing the circuit area and increasing the computation speed in implementing to hardware using the SEED algorithm of a 128-bit block cipher. SEED cipher can be implemented with S/W or H/W method. It should be important that we have minimize the area and computation time in H/W implementation. To increase the computation speed, we used the structure of the pipelined systolic array, and this structure is a simple thing without including any buffer at the input and output circuit. This circuit can record the encryption rate of 320 Mbps at 10 MHz clock. We have designed the circuit with the Verilog HDL coding showing the circuit performances in the figures and the table.

• Journal of IKEEE
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• 제22권3호
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• pp.846-849
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• 2018

Wireless power transfer (WPT) is the technology that enables the power to transmit electromagnetic field to an electrical load without the use of wires. There are two kinds of magnetic resonant coupling and inductive coupling ways transmitting from the source to the output load. Compared with microwave method for energy transfer over a long distance, the magnetic resonance method has the advantages of reducing the barrier of electromagnetic wave and enhancing the efficiency of power transmission. In this paper, the wireless power transfer circuit having a resonant frequency of 13.45 MHz for the low power system is studied, and the hardware implementation is accomplished to measure the power transmission efficiency for the distance between the transmitter and the receiver.

• Journal of Advanced Navigation Technology
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• 제15권2호
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• pp.281-286
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• 2011

Data sorting is one of important pre-process to utilize huge data in modern society, but sorting spends a lot of time by sorting itself. In this paper, we presented hybrid sorting algorithm that splits array to sort concurrently in CPU and GPU. To do this, we decided most effective range of array based on hardware performance, then accomplished reducing whole sorting time by concurrent sorting on CPU and GPU. As shown in results of experiment, hybrid sorting improved about eight percent of sorting time in comparison with the sorting time using only GPU.

• Journal of Communications and Networks
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• 제10권1호
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• pp.55-62
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• 2008

Bandpass sampling (BPS) techniques for the direct down-conversion of RF bandpass signals have become an essential technique for software defined radio (SDR), due to their advantage of minimizing the radio frequency (RF) front-end hardware dependency. This paper proposes an algorithm for finding the minimum BPS frequency for simultaneously down-converting multiple RF signals through full permutation over all the valid sampling ranges found for the multiple RF signals. We also present a scheme for reducing the computational complexity resulting from the large scale of the purmutation calculation involved in searching for the minimum BPS frequency. In addition, we investigate the BPS frequency allowing for the guard-band between adajacent down-converted signals, which help lessen the severe requirements in practical implementations. The performance of the proposed method is compared with those of other pre-reported methods to prove its effectiveness.

• Proceedings of the KSRS Conference
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• 대한원격탐사학회 2007년도 Proceedings of ISRS 2007
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• pp.101-104
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• 2007

Efficient Query processing and optimization are critical for reducing network traffic and decreasing latency of query when accessing and manipulating sensor data of large-scale sensor networks. Currently it has been studied in sensor database projects. These works have mainly focused on in-network query processing for sensor networks and assumes homogeneous sensor networks, where each sensor network has same hardware and software configuration. In this paper, we present a framework for efficient query processing over heterogeneous sensor networks. Our proposed framework introduces query processing paradigm considering two heterogeneous characteristics of sensor networks: (1) data dissemination approach such as push, pull, and hybrid; (2) query processing capability of sensor networks if they may support in-network aggregation, spatial, periodic and conditional operators. Additionally, we propose multi-query optimization strategies supporting cross-translation between data acquisition query and data stream query to minimize total cost of multiple queries. It has been implemented in WSN middleware, COSMOS, developed by ETRI.

• Journal of the Korean Society of Safety
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• 제20권1호
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• pp.137-142
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• 2005

This study aims to survey the fatal industrial accidents attributed to crane, and to present their preventive measures based on the results of the survey. The survey was on the basis of 60 fatal accidents caused by crane from January 1998 to July 2003. The results showed that 1) of varying types of crane, fatal accidents were most frequently caused by mobile no: 2) more crane accidents occurred on weekend of Friday and Saturday by a day of the week; 3) experienced crane operators with long length of work or the age of over 40 were more frequently subjected to fatal accidents compared to novice operators; and 4) crane accidents were more attributable to unsafe acts such as poor working method, non-observance for safe working rules, etc. than hardware aspects of crane itself. It is recommended that for reducing crane accidents, more practical education and training for crane operation be reinforced.

• Journal of Internet Computing and Services
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• 제7권1호
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• pp.49-57
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 12B-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array, This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.