Journal of Advanced Navigation Technology (한국항행학회논문지)

The Korean Navigation Institute (한국항행학회)
권호 표지
DOI QR코드

DOI QR Code

Designing Hybrid Sorting Algorithm for PC with GPU

GPU가 장착된 PC를 위한 혼합 정렬 알고리즘 설계

  • Kwon, Oh-Young (School of Computer Science & Engineering, Korea University of Technology and Education)
  • 권오영 (한국기술교육대학교 컴퓨터공학부)
  • Received : 2011.03.02
  • Accepted : 2011.04.30
  • Published : 2011.04.30
Download PDF
⟨ Previous Next ⟩

Abstract

Data sorting is one of important pre-process to utilize huge data in modern society, but sorting spends a lot of time by sorting itself. In this paper, we presented hybrid sorting algorithm that splits array to sort concurrently in CPU and GPU. To do this, we decided most effective range of array based on hardware performance, then accomplished reducing whole sorting time by concurrent sorting on CPU and GPU. As shown in results of experiment, hybrid sorting improved about eight percent of sorting time in comparison with the sorting time using only GPU.

데이터 정렬은 현대 사회에 존재하는 수많은 디지털 데이터에 대한 중요한 가공 작업 중의 하나이지만, 데이터가 방대할수록 정렬 과정 자체도 많은 연산시간을 소비한다. 본 논문에서 데이터 배열을 분할하여 PC에 있는 CPU와 GPU에서 각각 동시에 정렬을 수행하는 혼합 정렬 알고리즘을 제안하였다. 각 장치의 처리 성능을 바탕으로 가장 효율적인 배열의 분할 범위를 결정하고 각각 분할된 영역을 CPU와 GPU에서 동시에 정렬함으로써 전체 정렬 시간을 단축시켰다. 실험결과에서 알 수 있듯 혼합 정렬이 GPU만 활용한 정렬보다 8%이상 정렬 수행 속도를 향상시켰다.

Keywords

References

  1. N. Satish, M. Harris, and M. Garland, "Designing efficient sorting algorithms for manycore GPUs". Proc. 23rd IEEE Int'l Parallel & Distributed Processing Symposium, May 2009.
  2. N. K. Govindaraju, J. Gray, R. Kumar, and D. Manocha, "GPUTera Sort: High performance graphics coprocessor sorting for large database management", in Proc. 2006 ACM SIGMOD Int''l Conference on Management of Data, 2006, pp. 325-336.
  3. J. Chhugani, W. Macy, A. Baransi, A. D. Nguyen, M. Hagog, S. Kumar, V. W. Lee, Y.-K. Chen, and P. Dubey, "Efficient implementation of sorting on multi-core SIMD CPU architecture", in Proc. 34th Int'l Conference on Very Large Data Bases, Aug. 2008, pp. 1313-1324.
  4. F. Gavril, "Merging with parallel processors", Commun. ACM, vol. 18, no. 10, pp. 588-591, 1975. https://doi.org/10.1145/361020.361216
  5. NVIDIACorporation, "NVIDIA CUDA SDK", http://www.nvidia.com/cuda, 2009.
  6. NVIDIA CUDA Programming Guide, NVIDIA Corporation, Jun. 2008, version 2.0.
  7. J. Nickolls, I. Buck, M. Garland, and K. Skadron, "Scalable parallel programming with CUDA", Queue, vol. 6, no. 2, pp. 40-53, Mar/Apr 2008. https://doi.org/10.1145/1365490.1365500
  8. Tim Purcell, Craig Donner, Mike Cammarano, Henrik Wann Jensen, and Pat Hanrahan: "Photon Mapping on Programmable Graphics Hardware". Graphics Hardware 2003.
  9. Samuel Willams, Andrew Waterman, and David Patterson, "Roofline: an Insightful Visual Performance model for multicore architectures," Comm. of ACM, Vol. 52, Issue 4, Apr. 2009, pp. 65-76. https://doi.org/10.1145/1498765.1498785