• 한국정보전자통신기술학회논문지
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• 제2권4호
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• pp.45-51
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• 2009

DSP 시스템에서 널리 사용되는 힐버트 변환에서 곱셈 연산은 반드시 필요한 요소이며 변환에 사용되는 계수의 차수가 높아질수록 하드웨어는 복잡하고 많은 양의 게이트를 필요로 한다. 본 연구에서는 힐버트 변환에 사용되는 곱셈연산에 MAG 알고리즘이 적용된 쉬프트와 덧셈을 사용한 곱셈블록을 구현하여 하드웨어의 복잡도를 줄일 수 있다.

• Journal of applied mathematics & informatics
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• 제20권1_2호
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• pp.637-645
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• 2006

An adaptive algorithm for reducing the hardware complexity is presented. This paper proposes a simplified LMS algorithm for the adaptive system and analyzes its convergence characteristics mathematically. An objective of the proposed algorithm is to reduce the hardware complexity. In order to test the performances, it is applied to the echo canceller, and a program is described. The results from simulations show that the echo canceller adopting the proposed algorithm achieves almost the same performances as one adopting the NLMS algorithm. If an echo canceller is implemented with this algorithm, its computation quantities are reduced to the half as many as the one that is implemented with the LMS algorithm, without so much degradation of performances.

• ETRI Journal
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• 제32권5호
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• pp.657-664
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• 2010

Many embedded multimedia systems employ special hardware blocks to co-process with the main processor. Even though an efficient handling of such hardware blocks is critical on the overall performance of real-time multimedia systems, traditional real-time scheduling techniques cannot afford to guarantee a high quality of multimedia playbacks with neither delay nor jerking. This paper presents a hardware-aware rate monotonic scheduling (HA-RMS) algorithm to manage hardware tasks efficiently and handle special hardware blocks in the embedded multimedia system. The HA-RMS prioritizes the hardware tasks over software tasks not only to increase the hardware utilization of the system but also to reduce the output jitter of multimedia applications, which results in reducing the overall response time.

• 정보와 통신
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• 제25권12호
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• 한국컴퓨터산업학회논문지
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• 제2권2호
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• pp.211-218
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• 2001

본 논문에서는 동영상 부호화기에서 프레임 메모리 인터페이스의 하드웨어 구현을 위해 기존의 DRAM이 아닌 SDRAM을 사용하여 효율적인 메모리 맵의 구조를 제안한다. 동일한 버스에서도 효과적인 메모리 맵과 내부 버퍼 크기를 줄여 하드웨어 복잡도을 개선하고 내부 로직을 간략화하여 면적을 최소화하였다. 기존의 시스템은 매크로 블록 단위로 메모리에 저장하고 다시 출력을 위해서 랜덤하게 저장되어 있는 데이터를 액세스하여 많은 시간을 소비한다. 따라서 데이터를 라인 단위로 저장 및 처리하므로 메모리의 엑세스 시간을 효과적으로 줄일 수 있는 방법을 제시하였다.

• 전자공학회논문지B
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• 제31B권7호
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• pp.149-158
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• 1994

Recently the fuzzy control is widely used as a tool for constructing automatic control systems which can replace the manual operation of large-scale nonlinear plants. In most applications of the fuzzy control however it is hard to meet the requirement of the operation time. In some real-time control the fuzzy control scheme requires too much computing time for fuzzification inference and defuzzification. To reduce the computing time there may be two alternatives the development of a new operation algorithm and the design of high-speed fuzzy hardware. In this paper to solve the problem of reducing the fuzzy operation time we propose a new high-speed fuzzy hardware scheme which has merits of its generality and extensibility. Finally we verify the proposed fuzzy hardware.

• 전자공학회논문지B
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• 제32B권12호
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• pp.1624-1634
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• 1995

Conventional full search block matching algorithm for motion estimation is computationally intensive and the resulting hardware cost is very high. In this paper, we present an efficient block matching algorithm using a 16:1 subsampling technique, and describe its hardware design. The algorithm reduces the number of pixels in calculating the mean absolute difference at each search location, instead of reducing the search locations.The algorithm is an extension of the block mating algorithm with 4:1 subsampling proposed by Liu and Zaccarin such that the amount of computation is reduced by a fact of 4(16 compared to the full search block matching algorithm) while producing similar performance.The algorithm can efficiently be designed into a hardware for real-time applications.

• International journal of advanced smart convergence
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• 제1권2호
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• pp.12-15
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• 2012

Energy costs for operating and cooling computing resources in Cloud infrastructure have increased significantly up to the point where they would surpass the hardware purchasing costs. Thus, reducing the energy consumption can save a significant amount of management cost. One of major approach is removing hardware over-provisioning. In this paper, we propose a technique that facilitates power saving through reducing resource over provisioning based on virtualization technology. To this end, we use dynamic workload shaping to reschedule and redistribute job requests considering overall power consumption. In this paper, we present our approach to shape workloads dynamically and distribute them on virtual machines and physical machines through virtualization technology. We generated synthetic workload data and evaluated it in simulating and real implementation. Our simulated results demonstrate our approach outperforms to when not using no workload shaping methodology.

• Journal of Power Electronics
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• 제13권4호
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• pp.712-718
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• 2013

This paper proposes a control method for reducing the total harmonic distortion (THD) of the grid current of three-phase grid-connected inverter systems when the grid voltage is distorted. The THD of the grid current caused by grid voltage harmonics is derived by considering the phase delay and magnitude attenuation due to the hardware low-pass filter (LPF). The Cauchy-Schwarz inequality theory is used in order to search more easily for the minimum point of the THD. Both the gain and angle of the compensation voltage at the minimum point of the THD of the grid current are derived with the variation of cut-off frequencies of the hardware LPF. Simulation and experimental results show the validity of the proposed control methods.

• Journal of information and communication convergence engineering
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• 제2권2호
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• pp.89-92
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• 2004

An adaptive algorithm for reducing the hardware complexity is presented. This paper proposes a modified LMS algorithm for the adaptive system and analyzes its convergence characteristics mathematically. An objective of the proposed algorithm is to reduce the hardware complexity. In order to test the performances, it is applied to the echo canceller, and a program is described. The results from simulations show that the echo canceller adopting the proposed algorithm achieves almost the same performances as one adopting the NLMS algorithm. If an echo canceller is implemented with this algorithm, its computation quantities are reduced to the one third as many as the one that is implemented with the NLMS algorithm, without so much degradation of performances.