• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.361-370
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• 2008

NoC is adopted for data communication between processors and IPs in MPSoC system. NoC has an advantage of scalability in that system can be easily expanded just by adding switches. However, as the number of switches increases, chip area increases as well as data transfer latency. This paper proposes an architecture that can reduce the number of switches in the system by sharing network interfaces. To reduce NI area, the modules sharing network interface use a common buffer in network interface. Experimental results show that the chip area has been reduced by 46.5% and data transfer latency by 17.1%, respectively, compared to conventional architecture.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.320-321
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• 2018

A non-isolated high voltage gain bidirectional DC-DC converter for battery storage system has been presented in this paper. The topology is composed of boost converter and traditional SEPIC converter. The proposed converter can achieve higher voltage conversion ratio with reduced voltage and current stresses in the switches. In additional, a reduced number of components are included in this topology. The PSIM simulation is carried to validate the analysis and operation of the converter.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1552-1557
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• 2015

The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

• Journal of Power Electronics
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• v.15 no.1
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• pp.96-105
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• 2015

In recent years, the multilevel converters have been given more attention due to their modularity, reliability, failure management and multi stepped output waveform with less total harmonic distortion. This paper presents a novel symmetric multilevel inverter topology with reduced switching components to generate a high quality stepped sinusoidal voltage waveform. The series and parallel combinations of switches in the proposed topology reduce the total number of conducting switches in each level of output voltages. In addition, a comparison between the proposed topology with another topology from the literature is presented. To verify the proposed topology, the computer based simulation model is developed using MATLAB/Simulink and experimentally with a prototype model results are then compared.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.334-336
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• 2007

This paper proposes a novel RGB-LED (light emitting diode) backlight system, for 32" LCD TVs, accompanied by a new X-Y Channel drive method in which its row and column switches control the individual division screen. This proposed driving method is able to produce division drive effects such as image improvement and reduced power consumption. Not only that, the number of converter needed in this method, that is 1 with $4^*$(m+n) switches, is much fewer than that of cluster drive method, that is $4^*(m^*n)$.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.3
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• pp.247-255
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• 2013

In this paper, a soft switching DC-DC converter for AC module type photovoltaic (PV) module integrated converter is proposed. A push-pull converter is suitable for a low voltage PV AC module system because the step-up ratio of a high frequency transformer is high and the number of primary side switches is relatively small. However, the conventional push-pull converters do not have high efficiency because of high switching losses by hard switching and transformer losses (copper and iron losses) by high turns-ratio of the transformer. In the proposed converter, primary side switches are turned on at zero voltage switching (ZCS) condition and turned off at zero current switching (ZVS) condition through parallel resonance between secondary leakage inductance of the transformer and a resonant capacitor. Therefore the proposed push-pull converter decreases the switching loss using soft switching of the primary switches. Also, the turns-ratio of the transformer can be reduced by half using a voltage-doubler of secondary side. The theoretical analysis of the proposed converter is verified by simulation and experimental results.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.1001-1004
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• 2007

This paper proposes a novel RGB-LED (light emitting diode) backlight system, for 32" LCD TVs, accompanied by a new X-Y Channel driving method in which its row and column switches control the individual division screen. This proposed driving method is able to produce division driving effects such as image improvement and reduced power consumption. Not only that, the number of driver needed in this method, that is 3 power supplies with 3*(m+n) switches, is much fewer than that of cluster driving method, that is 3*(m*n) driver.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.105-107
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• 2018

This paper presents a new hybrid multilevel converter topology, which consists of a combination of the series connected switched capacitor units with boost ability, and an H-bridge with T-type bidirectional switches. The proposed converter boosts the input voltage without any bulky inductors, and has the small number of components, which can make the size and cost of a power converter greatly reduced. The output filter size and harmonics are also reduced by the high quality multilevel output. In addition, there is no need for complicated methods to balance the capacitor voltage. Simulation and experimental results with a nine-level converter system are presented to validate the proposed topology and modulation method.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.10
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• pp.807-821
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• 1991

A mulitpath MIN(Multistage Interconnection Network), CSMP(Chained Shuffle Multi-Path) network, is proposed, having fault-tolerance and dynamic reroutability. The number of stages and the number of links between adjacent stagges are the same as in single path MINs, so the overall hardware complexity is considerably reduced in comparison with other multipath MINs. The CSMP networks feature links between switches belonging to the same state, forming loops of switches. The network can tolerate multiple faults, up to (N/4)*(log$_2$N-1), having occured in any stages including the first and the last ones(N:NO. of input). To analyze reliability, terminal reliability (TR) and mean time to failure( MTTE) age given for the networks, and the TR figures are compared to those of other static and dynamic rerouting multipath MINs. Also the MTTE figures are compared. The performance of the proposed network with respect to its bandwidth (BW) and probability of acceptance(PA) is analyzed and is compared to that of other more complex multipath MINs. The cost efficiency analysis of reliability and performance shows that the network is more cost-effective than other previously proposed fault-tolerant multipath MINs.