• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.174-181
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• 2004

In this paper, we review the four receiver architectures and four methods for multi-standard receiver design. Propose reconfigurable RF block can be used for both low-IF and direct conversion architecture. Also, using reconfigurable mixer method, it can be operated at $2{\sim}6$ GHz range for multi-standard receiver. It consists of wideband mixer, filter, and automatic gain control amplifier and to get wide-band operation, $2{\sim}6$ GHz, wide-band mixer use flexible input matching method. Besides, to design multi-standard receiver, LNA bank that support each standard is necessary and it has good performance to compensate the performance of wide-band mixer. Finally, we design and simulate proposed reconfigurable RF block and to prove that it has acceptable performances for various wireless standards, the LNA bank that supports both IEEE 802.11a/b/g and WCDMA is also designed and simulated with it.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.9
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• pp.816-824
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• 2004

In this paper, the framework for accelerating the development of personal robots is presented, which includes the technology such as modularization with its own processing and standardization open to the other developers. Its basic elements are Module-D(Module of DRP I) characterized functionally and VM-D(Virtual Machine of DRP I) arbitrating Module-Ds. They can suggest the effective ways for integrating various robotic components and interfacing among them. Based on this framework, we developed a fully modularized personal robot called DRP I(Dynamically Reconfigurable Personal robot). Its hardware components are easily attached to and detached from the whole system. In addition, each software of the components is functionally distributed. For the materialization of the proposed idea, we mainly focus on the dynamically reconfigurable feature of DRP I.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.309-311
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• 2005

In general, for specific applications, customized hardware showed better performance than general processor in terms of processing time and power consumption. However, customized hardware systems have lacks of flexibility in nature and it leads the difficulties for debugging and architecture level revision for performance enhancement. To solve this problem, reconfigurable hardware is developed. Proposed reconfigurable hardware architecture for FIR filter system can easily change the architecture of filter blocks including filter tap size and their signal path. Proposed FIR filter architecture was implemented on FPGA using several MUXs and registers and it showed the reconfigurablility and reusability in several examples.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.418-429
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• 2018

This paper studies the decentralized position/force control problem for constrained reconfigurable manipulator without torque sensing. A novel joint torque estimation scheme that exploits the existing structural elasticity of the manipulator joint with harmonic drive model is applied for each joint module. Based on the estimated joint torque and dynamic output feedback technique, a decentralized position/force control strategy is presented. In order to solve the problem of controller parameter perturbation, the non-fragile robust technique is introduced into the dynamic output feedback controller. Subsequently, the stability of the closed-loop system is proved using the Lyapunov theory and linear matrix inequality (LMI) technique. Finally, two 2-DOF constrained reconfigurable manipulators with different configurations are applied to verify the effectiveness of the proposed control scheme in numerical simulation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.3
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.2
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• pp.63-70
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• 2019

To increase the efficiency of task on the desk, this paper proposes a reconfigurable desk. The proposed reconfigurable desk is based on the Pin Art technology. For the design of the proposed desk, the upper surface of the desk is divided into small units, and then the user easily controls the height of the divided pieces to make desk a desired shape by using the proposed user interface. The Arduino module controls the hardware and the user interface is configured by using Android applications, making it easy for anyone to use. Through extensive experiments, the proposed system shows that various types of deformations are possible and thus the utilization is very high by mounting diverse devices.

• Journal of Korea Society of Digital Industry and Information Management
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• v.14 no.4
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• pp.87-92
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• 2018

One of the problems with the base station equipment is that there is a large difference between the replacement time of the hardware equipment such as the base station equipment and the radio access equipment, and the evolution period of the communication standard. Therefore, the base station communication platform must be flexible enough to handle the evolving communication standards after purchase. Recent research on reconfigurable communications platforms has focused on the efficient architecture of the communications platform to meet these requirements through software downloads while still using existing hardware. This paper presents a prototype of a base station communications platform based on the ETSI standard reconfigurable architecture. The communication platform presented in this paper is implemented as an ETSI standard reconfigurable architecture using a general-purpose DSP (Digital Signal Processor). In the implemented prototype, we verify the real-time feasibility of communication protocol updates through software reconfiguration.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.95-96
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• 2013

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.757-758
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• 2013