• Journal of electromagnetic engineering and science
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• 제16권4호
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• pp.206-209
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• 2016

This letter proposes a reconfigurable directional coupler that uses a variable impedance mismatch reflector to achieve high isolation characteristics in the antenna front end. The reconfigurable coupler consists of a directional coupler and a single-pole four-throw (SP4T) switch with different load impedances as a variable load mismatch reflector. Selection of the load impedance by the reflector allows cancellation of the reflected signal due to antenna load mismatch and the leakage from the input to isolation port of the directional coupler, resulting in high isolation characteristics. The performance of the proposed architecture in separating the received (Rx) signal from the transmitted (Tx) signal in the antenna front end was verified by implementing and testing the reconfigurable coupler at 917 MHz for UHF radio-frequency identification (RFID) applications. The proposed reconfigurable directional coupler showed an improvement in the isolation characteristics of more than 20 dB at the operation frequency band.

• Proceedings of the Korea Information Processing Society Conference
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• 한국정보처리학회 2010년도 추계학술발표대회
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• pp.1555-1557
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• 2010

위성 탑재 소프트웨어는 기본적인 위성의 상태 데이터 획득에서부터 지상국과의 송수신 및 위성 고유의 임무 수행의 전 과정을 담당하고 있다. 이러한 위성 탑재 소프트웨어에 있어 무엇보다 강조되는 점이 신뢰성이며, 이를 위한 많은 연구가 진행되어 왔다. 위성 탑재 소프트웨어의 개발 과정에서 여러 단계의 검증 및 테스트가 수반되게 되며, 이러한 위성 탑재 소프트웨어의 개발에는 많은 시간과 노력이 요구된다. 또한, 위성의 소프트웨어는 그 특성상 위성 발사 후 탑재 소프트웨어에 대한 수정 및 개선에 많은 어려움이 따르게 된다. 본 연구에서는 위성 탑재 소프트웨어 개발 과정에서 재사용성을 높이고 소프트웨어 및 위성 임무 변경에 보다 용이하게 대응할 수 있는 Reconfigurable Software Architecture 를 제안한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제46권6호
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• pp.58-64
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• 2009

For the success of the reconfigurable computing, the algorithm for mapping operations onto coarse-grained reconfigurable architecture is very important. This paper proposes a resource-aware mapping system for the coarse-grained reconfigurable architecture and its own underlying heuristic algorithm. The operation assignment and the routing path allocation are simultaneously performed with a cycle-accurate time-exclusive resource model. The proposed algorithm minimizes the communication resource usage and the global memory access with the list scheduling heuristic. The operation to be mapped are prioritized with general properties of data flow. The evaluations of the proposed algorithm show that the performance is significantly enhanced in several benchmark applications.

• Journal of KIISE:Computer Systems and Theory
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• 제37권5호
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• pp.257-271
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• 2010

As the end of photolithographic integration era is approaching fast, numerous nanoscale devices and systems based on novel nanoscale materials and assembly techniques are recently emerging. Notably, various reconfigurable architectures with considerable promise have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high-density sys-tems consisting of nanometer-scale elements are likely to have numerous physical imperfections and variations. Therefore, defect-tolerance is considered as one of the most exigent challenges in nanowire crossbar systems. In this work, three different defect-avoidant logic mapping algorithms to circumvent defective crosspoints in nanowire reconfigurable crossbar systems are evaluated in terms of various performance metrics. Then, a novel method to find the most cost-effective repair solution is demonstrated by considering all major repair parameters and quantitatively estimating the performance and cost-effectiveness of each algorithm. Extensive parametric simulation results are reported to compare overall repair costs of the repair algorithms under consideration and to validate the cost-driven repair optimization technique.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 한국퍼지및지능시스템학회 2005년도 추계학술대회 학술발표 논문집 제15권 제2호
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• pp.500-503
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• 2005

Many researches on intelligent system have been performed and various intelligent algorithms have been developed, which are effective under an assumed specific environment and purpose. But in an real environment, the performance of these algorithms can be largely degraded. In this Paper, we Proposed an Evolvable and Reconfigurable(ERI) Architecture based on intelligent Macro Core(IMC) so that various and new algorithms can be easily added incrementally and construct the reconfigured intelligent system easily. We apply the proposed ERI Architecture to face detection and recognition system to show its usefulness.

• Journal of the Korean Institute of Intelligent Systems
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• 제15권7호
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• pp.823-827
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• 2005

Many researches on intelligent system have been performed and various intelligent algorithms have been developed, which are effective under an assumed specific environment and purpose. But in an real environment, the Performance of these algorithms can be largely degraded. In this paper, we proposed an Evolvable and Reconfigurable(ERI) Architecture based on intelligent Macro Core(IMC) so that various and new algorithms can be easily added incrementally and construct the reconfigured intelligent system easily. We apply the proposed ERI Architecture to face detection and recognition system to show its usefulness.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.318-328
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• 2011

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.663-664
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• 2006

This paper presents a reconfigurable digital signal processing(rDSP) architecture that is effective for implementing adaptive digital signal processing in the applications of smart health care system. This rDSP architecture employs an evolution capability of FIR filters using genetic algorithm. Parallel genetic algorithm based rDSP architecture evolves FIR filters to explore optimal configuration of filter combination, associated parameters, and structure of feature space adaptively to noisy environments for an adaptive signal processing. The proposed DSP architecture is implemented using Xilinx Virtex4 FPGA device and SMIC 0.18um CMOS Technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.284-299
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• 2014

Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel level parallelism (KLP). However, the existing CGRA-based multi-core architectures suffer from much energy and performance bottleneck when trying to exploit the KLP because of poor resource utilization caused by insufficient flexibility. In this work, we propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilization focusing on the kernel-stream type of the KLP. In addition, based on the RSF, we introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream on CGRA-based multi-core architectures. Experimental results show that the proposed approaches improve performance by up to 50.62 times and reduce energy by up to 50.16% when compared with the conventional CGRA-based multi-core architectures.

• IEMEK Journal of Embedded Systems and Applications
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• 제2권4호
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• pp.242-250
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• 2007

Wireless sensor networks are subject to highly heterogeneous system requirements in terms of their functionality and performance due to their broad application areas. Though the heterogeneity hinders the opportunity of developing a single universal platform for sensor networks, efforts to provide uniform, inter-operable and scalable ones for sensor networks are still essential for the growth of the industry as well as their technological advance. As a part of our work to develop such a robust platform, this paper presents the software architecture for sensor nodes with focus on our sensor node operating system and its configuration methodology. Addressing principle issues in its design space which includes programming, execution, task scheduling and software layer models, our architecture is highly reconfigurable with respect to system resources and functional requirements and also highly efficient in supporting multi-threading under small system resources.