• The Journal of the Acoustical Society of Korea
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• v.15 no.3E
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• pp.13-18
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• 1996

A real-time identifier for the nonstationary time-varying signals and systems was implemented using a low cost DSP (digital signal processing) chip. The identifier is comprised of I/O units, a central processing unit, a control unit and its supporting software. In order t estimate the system accurately and to reduce quantization error during arithmetic operation, the firmware was programmed with 64-bit extended precision arithmetic. The performance of the identifier was verified by comparing with the simulation results. The implemented real-time identifier has negligible quantization errors and its real-time processing capability crresponds to 0.6kHz for the nonstationary AR (autoregressive) model with n=4 and m=1.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.2
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• pp.145-150
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• 1999

A real-time control system, composed of the controlled processor and the controller computer(s), may have a variety of task types, some of which have tight timing-constraints in generating the correct control input. The maximum period of those task failures tolerable by the system is called the hard deadline, which depends on not only fault characteristics but also task characteristics. In the paper, we extend a method deriving the hard deadline in LTI system executing single task. An algorithm to combine the deadlines of all the elementary tasks in the same operation-mode is proposed to derive the hard deadline of the entire system. For the end, we modify the state equation for the task to capture the effects of task failures (delays in producing correct values) and inter-correlation. We also classify the type of executing the tasks according to operation modes associated with relative importance of correlated levels among tasks, into series, parallel, and cascade modes. Some examples are presented to demonstrate the effectiveness of the proposed methods.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.6
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• pp.626-631
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• 1997

This paper represents the design of a real-time image preprocessing system. The preprocessing system performs hardware-wise mask operations and thresholding operations at the speed of camera output single rate. The preprocessing system consists of the preprocessing board and the main processing board. The preprocessing board includes preprocessing unit that includes a $5\times5$ mask processor and LUT, and can perform mask and threshold operations in real-time. To achieve high-resolution image input data($20485\timesn$), the preprocessing board has a linescan camera interface. The main processing board includes the image processor unit and main processor unit. The image processor unit is equipped with TI's TMS320C32 DSP and can perform image processing algorithms at high speed. The main processor unit controls the operation of total system. The proposed system is faster than the conventional CPU based system.

• Journal of Korea Multimedia Society
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• v.21 no.2
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• pp.232-241
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• 2018

Operational Transformation (OT) algorithms for real-time collaborative editing systems are becoming increasingly important due to the increased demand for collaborative data processing. The operational transformation algorithm is a technique for real-time concurrency control and consistency maintenance with non-locking technique, and many studies have been conducted to overcome three issues of convergence, causality-prevention, and intention-prevention. However, previous work has the disadvantage of wasting memory by storing all operations that occurred during an edit operation in the history buffer to solve this problem. Therefore, we propose a memory-saving real-time collaborative editing system that maintains a constant memory space and concurrency control through a method of applying the valid-time to each user-generated operation in order to reduce memory waste. This system prevents long-term memory occupation of client-generated operations, thus it reduces the space and time complexity even with low-rate of collaboration work, so that the performance degradation avoids.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.9
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• pp.101-108
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• 2007

State estimators are used to monitor the operating states of power systems in modern EMS. It iteratively calculates the voltage profile of the currently operating power system with voltage, current, and power measurements gathered from the entire system. All the measurements are usually assumed to be obtained simultaneously. It is practically impossible, however, to maintain the synchronism of the measurement data. Recently, phasor measurements synchronized via satellite are used for the operation of these power systems. This paper describes the modified state estimator used to support the processing of synchronized phasor measurements. Synchronized phasor measurements are found to provide synchronism of measurement data and improve the accuracy/redundancy of the measurement data for state estimation. The details of the developed state estimation program and some numerical results of operation are presented.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.8
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• pp.718-725
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• 2004

The real-time industrial network, often referred to as fieldbus, is an important element for intelligent manufacturing systems. Thus, in order to satisfy the real-time requirements of field devices, numerous fieldbus protocols have been announced. But, the application of fieldbus has been limited due to the high cost of hardware and the difficulty in interfacing with multi-vendor products. Therefore, as an alternative to fieldbus, the computer network technology, especially Ethernet (IEEE 802.3), is being adapted to the industrial environment. However, the crucial technical obstacle for Ethernet is its non-deterministic behavior that makes it inadequate for industrial applications where real-time data have to be delivered within a certain time limit. Recently, the development of switched Ethernet shows a very promising prospect for industrial application due to the elimination of uncertainties in the network operation resulting in much improved performance. This paper focuses on the application of the switched Ethernet with cascade structure for industrial communications. More specifically, this paper presents an analytical performance evaluation of switched Ethernet with cascade structure, and a case study about networked control system.

• Nuclear Engineering and Technology
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• v.55 no.8
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• pp.2952-2965
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• 2023

Advanced reactors, such as Small Modular Reactors or existing Nuclear Power Plants, often use Field Programmable Gate Array (FPGA) based controllers in new Instrumentation and Control (I&C) system architectures or as an alternative to existing analog-based I&C systems. Compared to CPU-based Programmable Logic Controllers (PLCs), FPGAs offer better overall performance. However, programming functions on FPGAs can be challenging due to the requirement for a hardware description language that does not explicitly support the operation of real numbers. This study aims to implement the Reactor Trip (RT) functions of the existing analog-based Reactor Protection System (RPS) using FPGAs. The RT equations for Overtemperature delta Temperature and Overpower delta Temperature involve dynamic compensators expressed with the Laplace transform variable, 's', which is not directly supported by FPGAs. To address this issue, the trip equations with the Laplace variable in the continuous-time domain are transformed to the discrete-time domain using the Z-transform. Additionally, a new operation based on a relative value for the equation range is introduced for the handling of real numbers in the RT functions. The proposed approach can be utilized for upgrading the existing analog-based RPS as well as digitalizing control systems in advanced reactor systems.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 1999.10a
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• pp.121-130
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• 1999

The objective of this paper is to apply Extended AND-OR Graph (EAOG)-related techniques to extract knowledge from a specific problem-domain and perform analysis in complicated decision making area. Expert systems use expertise about a specific domain as their primary source of solving problems belonging to that domain. However, such expertise is complicated as well as uncertain, because most knowledge is expressed in causal relationships between concepts or variables. Therefore, if expert systems can be used effectively to provide more intelligent support for decision making in complicated specific problems, it should be equipped with real-time inference mechanism. We develop two kinds of EAOG-driven inference mechanisms(1) EAOG-based forward chaining and (2) EAOG-based backward chaining. and The EAOG method processes the following three characteristics. 1. Real-time inference : The EAOG inference mechanism is suitable for the real-time inference because its computational mechanism is based on matrix computation. 2. Matrix operation : All the subjective knowledge is delineated in a matrix form, so that inference process can proceed based on the matrix operation which is computationally efficient. 3. Bi-directional inference : Traditional inference method of expert systems is based on either forward chaining or backward chaining which is mutually exclusive in terms of logical process and computational efficiency. However, the proposed EAOG inference mechanism is generically bi-directional without loss of both speed and efficiency.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.125-134
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• 1994

In real-time database systems, transactions's commitment done before the given deadlines is more important than just getting the maximum throughput. Transactions missing the given deadlines are no longer meaningful in real-time applications. Therefore, there is a need for new transaction processing models to meet the given deadlines in real-time database applications, because moat conventional transaction models are not designed to meet deadlines. In this paper we propose a new transaction models which uses multiple versions of a data item. The model uses read-from graphs and dynamic reorder of transactions to meet deadlines. A read-from graph contains the past read semantics of read operations and support the model to decide which database operation to be taken. Then, we show simulation results comparing the proposed model with other transaction models such as two phase locking model and the optimistic concurrency control model.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.121-130
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• 2017

NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that does not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read/write operation is a page and the unit of erase operation is a block. Therefore, erase operation is slower than other operations. The AGC, the proposed garbage collection policy focuses on not only garbage collection time reduction for real-time guarantee but also wear-leveling for a flash memory lifetime. In order to achieve above goals, we define three garbage collection operating modes: Fast Mode, Smart Mode, and Wear-leveling Mode. The proposed policy decides the garbage collection mode depending on system CPU usage rate. Fast Mode selects the dirtiest block as victim block to minimize the erase operation time. However, Smart Mode selects the victim block by reflecting the invalid page number and block erase count to minimizing the erase operation time and deviation of block erase count. Wear-leveling Mode operates similar to Smart Mode and it makes groups and relocates the pages which has the similar update time. We implemented the proposed policy and measured the performance compare with the existing policies. Simulation results show that the proposed policy performs better than Cost-benefit policy with the 55% reduction in the operation time. Also, it performs better than Greedy policy with the 87% reduction in the deviation of erase count. Most of all, the proposed policy works adaptively according to the CPU usage rate, and guarantees the real-time performance of the system.