• Title/Summary/Keyword: Rasterization algorithm

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Implementation of a 'Rasterization based on Vector Algorithm' suited for a Multi-thread Shader architecture (Multi-Thread 쉐이더 구조에 적합한 Vector 기반의 Rasterization 알고리즘의 구현)

  • Lee, Ju-Suk;Kim, Woo-Young;Lee, Bo-Haeng;Lee, Kwang-Yeob
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.10
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    • pp.46-52
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    • 2009
  • A Multi-Core/Multi-Thread architecture is adopted for the Shader processor to enhance the processing performance. The Shader processor is designed to utilize its processing core IP for multiple purposes, such as Vertex-Shading, Rasterization, Pixel-Shading, etc. In this paper, we propose a 'Rasterization based on Vector Algorithm' that makes parallel pixels processing possible with Multi-Core and Multi-Thread architecture on the Shader Core. The proposed algorithm takes only 2% operation counts of the Scan-Line Algorithm and processes pixels independently.

Implementation and Performance Evaluation of Vector based Rasterization Algorithm using a Many-Core Processor (매니코어 프로세서를 이용한 벡터 기반 래스터화 알고리즘 구현 및 성능평가)

  • Shon, Dong-Koo;Kim, Jong-Myon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.8 no.2
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    • pp.87-93
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    • 2013
  • In this paper, we implemented and evaluated the performance of a vector-based rasterization algorithm of 3D graphics using a SIMD-based many-core processor that consists of 4,096 processing elements. In addition, we compared the performance and efficiency of the rasterization algorithm using the many-core processor and commercial GPU (Graphics Processing Unit) system which consists of 7 GPUs and each of which have 512 cores. Experimental results showed that the SIMD-based many-core processor outperforms the commercial GPU system in terms of execution time (3.13x speedup), energy efficiency (17.5x better), and area efficiency (13.3x better). These results demonstrate that the SIMD-based many-core processor has potential as an embedded mobile processor.

A Study on Replacing Method Global Illumination Using Ambient Occlusion (Ambient Occlusion을 이용한 Global Illumination 대체기법 연구)

  • Park, Jae-Wook;Kim, Yun-Jung
    • Cartoon and Animation Studies
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    • s.36
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    • pp.493-510
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    • 2014
  • From game consoles to TV and Hollywood films, 3D rendering technology is involved in various fields. Up until the late 90s, the computer image rendering method was rasterization that mainly used Phong Shading, and up until recently it was the go-to method for movies and film animation. In the 21st century, the quality provided by Ray Tracing and the development of Global Illumination was much more realistic and thus became popularized. However, despite its growing use in architectural rendering to the markets, Global Illumination in film animation and movies was limited due to its long render time. So, in this thesis, if one were to take the concept from each rendering method and consider it from a mathematical perspective, one could adapt the Ambient Occlusion's equation to the illumination loop equation used in rasterization. This algorithm modification has the capability to reflect the lighting of a diverse array of colors, like in Global Illumination, with a fast render time, as in rasterization, and the example RenderMan Shader is based upon this new algorithm. In conclusion, with Global Illumination's naturalistic lighting and rasterization's rendering speed, the combination of the best points of each is a new method with a short rendering time while producing good quality. I hope animations and films can benefit from this algorithm by the reduction of budget with an overall better quality output in VFX production.

Architecture Exploration of Optimal Many-Core Processors for a Vector-based Rasterization Algorithm (래스터화 알고리즘을 위한 최적의 매니코어 프로세서 구조 탐색)

  • Son, Dong-Koo;Kim, Cheol-Hong;Kim, Jong-Myon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.9 no.1
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    • pp.17-24
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    • 2014
  • In this paper, we implement and evaluate the performance of a vector-based rasterization algorithm for 3D graphics by using a SIMD (single instruction multiple data) many-core processor architecture. In addition, we evaluate the impact of a data-per-processing elements (DPE) ratio that is defined as the amount of data directly mapped to each processing element (PE) within many-core in terms of performance, energy efficiency, and area efficiency. For the experiment, we utilize seven different PE configurations by varying the DPE ratio (or the number PEs), which are implemented in the same 130 nm CMOS technology with a 500 MHz clock frequency. Experimental results indicate that the optimal PE configuration is achieved as the DPE ratio is in the range from 16,384 to 256 (or the number of PEs is in the range from 16 and 1,024), which meets the requirements of mobile devices in terms of the optimal performance and efficiency.

Analysis of Performance and Energy Efficiency of Core Mapping for Rasterization Algorithm using CUDA (CUDA를 이용한 Rasterization 알고리즘의 코어 매핑에 따른 성능 및 에너지 효율 분석)

  • Park, Min-Ho;Kim, Jong-Myon
    • Proceedings of the Korea Information Processing Society Conference
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    • 2013.05a
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    • pp.140-143
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    • 2013
  • 본 논문에서는 데이터 병렬성이 뛰어난 벡터 기반의 Rasterization 알고리즘을 CUDA를 이용하여 코어 매핑에 따른 성능 및 에너지 효율을 분석해 보았다. 블록 사이즈를 동일하게 맞춘 후 블록의 차원을 변경 하는 방법과 블록 사이즈를 변경하는 방법을 사용하여 실험하였다. 모의실험결과, 블록 사이즈가 동일할 때는 오차 범위 내로 동일한 성능과 에너지 효율을 보였다. 아키텍처마다 모든 자원을 사용할수 있는 이론적인 블록 및 스레드 구조가 존재하지만 메모리 접근에 대한 최적화를 이루어 내지 못한다면 Amdahl's law에 의해 성능 향상에 한계가 있다는 것을 확인하였다.

Development of a CAD-based Utility for Topological Identification and Rasterized Mapping from Polygonal Vector Data (CAD 수단을 이용한 벡터형 공간자료의 위상 검출과 격자도면화를 위한 유틸리티 개발)

  • 조동범;임재현
    • Journal of the Korean Institute of Landscape Architecture
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    • v.27 no.4
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    • pp.137-142
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    • 1999
  • The purpose of this study is to develope a CAD-based tool for rasterization of polygonal vector map in AutoCAD. To identity the layer property of polygonal entity with user-defined coordinates as topology, algorithm in processing entity data of selection set that intersected with scan line was used, and the layers were extracted sequentially by sorted intersecting points in data-list. In addition to the functions for querying and modifying topology, two options for mapping were set up to construct plan projection type and to change meshes' properties in existing DTM data. In case of plan projection type, user-defined cell size of 3DFACE mesh is available for more detailed edge, and topological draping on landform can be executed in case of referring DTM data as an AutoCAD's drawing. The concept of algorithm was simple and clear, but some unexpectable errors were found in detecting intersected coordinates that were AutoCAD's error, not the utility's. Also, the routines to check these errors were included in algorithmic processing. Developed utility named MESHMAP was written in entity data control functions of AutoLISP language and dialog control language(DCL) for the purpose of user-oriented interactive usage. MESHMAP was proved to be more effective in data handling and time comparing with GRIDMAP module in LANDCADD which has similar function.

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Implementation of Real-time Interactive Ray Tracing on GPU (GPU 기반의 실시간 인터렉티브 광선추적법 구현)

  • Bae, Sung-Min;Hong, Hyun-Ki
    • Journal of Korea Game Society
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    • v.7 no.3
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    • pp.59-66
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    • 2007
  • Ray tracing is one of the classical global illumination methods to generate a photo-realistic rendering image with various lighting effects such as reflection and refraction. However, there are some restrictions on real-time applications because of its computation load. In order to overcome these limitations, many researches of the ray tracing based on GPU (Graphics Processing Unit) have been presented up to now. In this paper, we implement the ray tracing algorithm by J. Purcell and combine it with two methods in order to improve the rendering performance for interactive applications. First, intersection points of the primary ray are determined efficiently using rasterization on graphics hardware. We then construct the acceleration structure of 3D objects to improve the rendering performance. There are few researches on a detail analysis of improved performance by these considerations in ray tracing rendering. We compare the rendering system with environment mapping based on GPU and implement the wireless remote rendering system. This system is useful for interactive applications such as the realtime composition, augmented reality and virtual reality.

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Real-Time Motion Blur using Approximated Motion Trails (이동궤적 근사 다면체를 이용한 실시간 모션블러 기법)

  • Hong, MinhPhuoc;Choi, Jinhyung;Oh, Kyoungsu
    • Journal of Korea Game Society
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    • v.17 no.1
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    • pp.17-26
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    • 2017
  • Several algorithms have been introduced to render motion blur in real time by solving the visibility problem in the spatio-temporal domains. However, some algorithms render at interactive frame rates but have artifacts or noise. Therefore, we propose a new algorithm that renders real-time motion blur using extruded triangles. Our method uses two triangles in the previous and the current frame to make an extruded triangle then send it to the rasterization. To solve the occlusion between extruded triangles for a given pixel, we introduce a combining solution using a sorting in front to back order and bitwise operations in the spatio-temporal dimensions.

A Design of Hierarchical Tile-based Rasterizer Using The Improved Tiling Algorithm (타일링 속도를 개선한 계층 구조 타일 기반 Rasterizer 설계)

  • Kim, Do-Hyun;Kyung, Gyu-Taek;Kwak, Jae-Chang;Lee, Kwang-yeob
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.309-311
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    • 2014
  • The tile-based rendering technique which divides the screen area into tiles of a specific size and creates a 3D graphic model of one tile at a time is used to efficiently utilize limited resources in a 3D graphic pipeline. In this paper, the tiling speed of tile-based rendering was improved by reducing the count of calling lower-levels in the hierarchical tile-based rendering technique. The tiling speed of the proposed Rasterizer is 13.030ms which is 56% faster than 29.614ms of multi-sort tiling and 24% faster than 17.208ms of the conventional hierarchical tiling technique.

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