• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.1009-1015
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• 2014

Chalcopyrite $CuInSe_2$ (CIS) thin films were prepared without Se- / S-containing gas by co-sputtering using $CuSe_2$ and $InSe_2$ selenide-targets and rapid thermal annealing. The grain size increased to a maximum of 54.68 nm with a predominant (112) plane. The tetragonal distortion parameter ${\eta}$ decreased and the inter-planar spacing $d_{(112)}$ increased in the RTA-treated CIS thin films annealed at a $400^{\circ}C$, which indicates better crystal quality. The increased carrier concentration of RTA-treated p-type CIS thin films led to a decrease in resistivity due to an increase in Cu composition at annealing temperatures ${\geq}350^{\circ}C$. The optical band gap energy ($E_g$) of CIS thin films decreased to 1.127 eV in RTA-treated CIS thin films annealed at $400^{\circ}C$ due to the improved crystallinity, elevated carrier concentration and decreased In composition.

• Journal of the Korean institute of surface engineering
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• v.38 no.3
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• pp.89-94
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• 2005

We investigate the reaction stability of cobalt and nickel with side-wall materials of $SiO_2\;and\;Si_3N_4$. We deposited 15nm-Co and 15nm-Ni on $SiO_2(200nm)/p-type$ Si(100) and $Si_3N_4(70 nm)/p-type$ Si(100). The samples were annealed at the temperatures of $700\~1100^{\circ}C$ for 40 seconds with a rapid thermal annealer. The sheet resistance, shape, and composition of the residual materials were investigated with a 4-points probe, a field emission scanning electron microscopy, and an AES depth profiling, respectively. Samples of annealed above $1000^{\circ}C$ showed the agglomeration of residual metals with maze shape and revealed extremely high sheet resistance. The Auger depth profiling showed that the $SiO_2$ substrates had no residual metallic scums after $H_2SO_4$ cleaning while $Si_3N_4$ substrates showed some metallic residuals. Therefore, the $SiO_2$ spacer may be appropriate than $Si_3N_4$ for newly proposed Co/Ni composite salicide process.

• Korean Journal of Materials Research
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• v.8 no.4
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• pp.323-327
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• 1998

All solid state lithium based rechargeable batteries were fabricated in a cell structure of Li/PEO-$LiCIO_4$-PC /$LIMn_2O_4$$LIMn_2O_4$ thin films were prepared by RF magnetron sputtering and the spinel structure could be obtained by Rapid Thermal Annealing (RT A) process at the temperature of around 750$750^{\circ}C$ . Room temperature cycling of this cell showed a nearly constant cell potential of 4 V( us. Li) and good reversibility.

• Current Photovoltaic Research
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• v.9 no.4
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• pp.137-144
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• 2021

In this study, the microstructure of the CVD-fabricated Cu(In,Ga)Se₂ (CIGSe) absorber layer by simulating the stacking sequence used in a co-evaporation method, and changes solar cell performance were investigated. The absorber layer prepared by stacking CuSe and (In,Ga)Se between InSe is separated into Ga-free CuInSe₂ and Ga-rich CIGSe, and transformed to CIGSe by selenization heat treatment with slight improvement in the the solar cell efficiency. However, in CVD, since the supply of liquid Cu-Se is not as active as in the co-evaporation method, the nanoocrystalline layer containing a large amount of Ga remained independently in the absorption layer, which acted as a cause of the loss of J_SC and FF. Therefore, by using a precursor structure in which CuGa is sputter-deposited on a single layer of InSe deposited by CVD, performance parameters of V_OC, J_SC, and FF could be greatly improved.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.3
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• pp.286-291
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• 2023

Perovskite materials are promising candidates for next-generation optoelectronic devices owing to their outstanding external quantum efficiency, high color purity, and ability to tune the light emission wavelength. However, conventional thermal annealing processes caused the degradation of perovskite, resulting in poor optoelectronic properties and a short lifetime. Herein, we propose a laser-induced recrystallization of perovskite thin film to enhance its light-emitting properties. Laser-induced recrystallization process was performed using rapid and instantaneous laser heating, which successfully induced grain growth of the perovskite material. The laser processing conditions were thoroughly optimized based on theoretical calculations and various material analyses such as x-ray diffraction, scanning electron microscope, and photoluminescence spectroscopy.

• The Bulletin of The Korean Astronomical Society
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• v.44 no.2
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• pp.60.4-60.4
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• 2019

Small bodies in the solar system are pristine leftovers of planetesimals since the formation epoch (~4.6 Gyr ago). After the formation, icy planetesimals have been preserved in the distant cold place beyond 30 au (i.e., Trans-Neptunian region) until recently without any catastrophic processes but have just been injected into inner region (<~5 au from the Sun) to be observed as comets. On the contrary, asteroids are rocky primitive objects (although some of them contains icy volatiles) distributing in the mainbelt between Mars and Jupiter orbits. Because of frequent encounters in the mainbelt, asteroids have experienced a number of repeated impacts until the present day. Namely, it is important to investigate thermal alternation process of cometary volatiles and refractories in the solar radiation field, whereas collisional and subsequence phenomena of asteroidal bodies. Although recent spacecraft observations revealed the physical natures on the surfaces of comets and asteroids, their interiors still remain largely unexplored. It is likely that a sudden brightening of a comet is associated with rapid sublimation of internal CO and CO2 or phase transition of amorphous H2O. An episodic dust ejection from an asteroid is causally related to an impact among asteroids, sudden sublimation of remaining subsurficial volatiles, etc. Because these transient phenomena provide rare opportunities to investigate their interiors, immediate observations using any optical instruments are particular important. In my presentation, I will review some examples of such transient phenomena in the solar system and propose possible collaborative research using the Korean Small Telescope Network.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.202-208
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• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.

• Journal of the Korean Vacuum Society
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• v.11 no.3
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• pp.151-158
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• 2002

Fabricated were ultra-shallow $p^+-n$ junctions on n-type Si(100) substrates using decaborane $(B_{10}H_{14})$ ion implantation. Decaborane ions were implanted at the acceleration voltages of 5 kV to 10 kV and at the dosages of $1\times10^{12}\textrm{cm}^2$.The implanted specimens were annealed at $800^{\circ}C$, $900^{\circ}C$ and $1000^{\circ}C$ for 10 s in $N_2$ atmosphere through a rapid thermal process. From the measurement of the implantation-induced damages through $2MeV^4 He^{2+}$ channeling spectra, the implanted specimen at the acceleration voltage of 15 kV showed higher backscattering yield than those of the bare n-type Si wafer and the implanted specimens at 5 kV and 10 kV. From the channeling spectra, the calculated thicknesses of amorphous layers induced by the ioin implantation at the acceleration voltages of 5 kV, 10 kV and 15 kV were 1.9 nm, 2.5 nm and 4.3 nm, respectively. After annealing at $800^{\circ}C$ for 10 s in $N_2$ atmosphere, most implantation-induced damages of the specimens implanted at the acceleration voltage of 10 kV were recovered and they exhibited the same channeling yield as the bare Si wafer. In this case, the calculated thickness of the amorphous layer was 0.98 nm. Hall measurements and sheet resistance measurements showed that the dopant activation increased with implantation energy, ion dosage and annealing temperature. From the current-voltage measurement, it is observed that leakage current density is decreased with the increase of annealing temperature and implantation energy.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.1
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• pp.25-32
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• 2007

We investigated the silicide reaction stability between 10 nm-Col-xNix alloy films and silicon substrates with the existence of 4 nm-thick natural oxide layers. We thermally evaporated 10 nm-Col-xNix alloy films by varying $x=0.1{\sim}0.9$ on naturally oxidized single crystal and 70 nm-thick polycrystalline silicon substrates. The films structures were annealed by rapid thermal annealing (RTA) from $600^{\circ}C$ to $1100^{\circ}C$ for 40 seconds with the purpose of silicidation. After the removal of residual metallic residue with sulfuric acid, the sheet resistance, microstructure, composition, and surface roughness were investigated using a four-point probe, a field emission scanning electron microscope, a field ion bean4 an X-ray diffractometer, and an Auger electron depth profiling spectroscope, respectively, to confirm the silicide reaction. The residual stress of silicon substrate was also analyzed using a micro-Raman spectrometer We report that the silicide reaction does not occur if natural oxides are present. Metallic oxide residues may be present on a polysilicon substrate at high silicidation temperatures. Huge residual stress is possible on a single crystal silicon substrate at high temperature, and these may result in micro-pinholes. Our results imply that the natural oxide layer removal process is of importance to ensure the successful completion of the silicide process with CoNi alloy films.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.16-22
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• 2008

We fabricated thermally-evaporated 10 nm-Ni/30 nm and 70 nm Poly-Si/200 nm-$SiO_2/Si$ structures to investigate the thermal stability of nickel silicides formed by rapid thermal annealing(RTA) of the temperature of $300{\sim}1100^{\circ}C$ for 40 seconds. We employed for a four-point tester, field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), high resolution X-ray diffraction(HRIXRD), and scanning probe microscope(SPM) in order to examine the sheet resistance, in-plane microstructure, cross-sectional microstructure evolution, phase transformation, and surface roughness, respectively. The silicide on 30 nm polysilicon substrate was stable at temperature up to $900^{\circ}C$, while the one on 70 nm substrate showed the conventional $NiSi_2$ transformation temperature of $700^{\circ}C$. The HRXRD result also supported the existence of NiSi-phase up to $900^{\circ}C$ for the Ni silicide on the 30 nm polysilicon substrate. FE-SEM and TEM confirmed that 40 nm thick uniform silicide layer and island-like agglomerated silicide phase of $1{\mu}m$ pitch without residual polysilicon were formed on 30 nm polysilicon substrate at $700^{\circ}C\;and\;1000^{\circ}C$, respectively. All silicides were nonuniform and formed on top of the residual polysilicon for 70 nm polysilicon substrates. Through SPM analysis, we confirmed the surface roughness was below 17 nm, which implied the advantage on FUSI gate of CMOS process. Our results imply that we may tune the thermal stability of nickel monosilicide by reducing the height of polysilicon gate.