• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.454-461
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• 2015

Light enhancement of GaN based light emitting diodes (LEDs) have been investigated by texturing the top p-GaN surface. Nano-textured LEDs have been fabricated using self-assembled Ni nano mask during dry etching process. Experimental results were further compared with simulation data. Three types of LEDs were fabricated: Conventional (planar LED), Surface nano-porous (porous LED) and Surface nano-cluster (cluster LED). Compared to planar LED there were about 100% and 54% enhancement of light output power for porous and cluster LED respectively at an injection current of 20 mA. Moreover, simulation result showed consistency with experimental result. The increased probability of light scattering at the nano-textured GaN-air interface is the major reason for increasing the light extraction efficiency.

• 한국세라믹학회지
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• 제31권12호
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• pp.1501-1506
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• 1994

The precipitate of FeCl2.4H2O and NaOH, Fe(OH)2 was rapidly made to oxidize by H2O2 to prepare $\delta$-FeOOH. The particle size, surface and morphology of $\delta$-FeOOH, and the shape and structure of thermally decomposed $\delta$-FeOOH were investigated by the use of high resolution STEM. $\delta$-FeOOH prepared under the condition of reaction temperature of Fe(OH)2 at 4$0^{\circ}C$, [OH-][Fe2+]=5 and aging time of 2 hr Fe(OH)2, had 630$\AA$ mean particle size, 4~5 aspect ratio, 20.8 emu/g saturation magnetization and 210 Oe coercivity. The edges of $\delta$-FeOOH were inclined to (001) about 41$^{\circ}$, 60$^{\circ}$ and coincident with (102), (101) respectively. When $\delta$-FeOOH was thermally decomposed at 25$0^{\circ}C$ for 2 hr in vacuo, which had micropores of 0.9 nm thickness and crystallites of 2.4 nm thickness. (001)hex, [10]hex. of $\delta$-FeOOH parallel with (001)hex, [100]hex. of $\alpha$-Fe2O3 respectively. This showed three dimensional topotaxial structure transition, which was investigated by SADP (Selected Area Diffraction Pattern) of STEM.

• 한국결정성장학회지
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• 제6권3호
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• pp.424-430
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• 1996

태양전지의 공정중 고온공정을 줄여줌으로서 최종 태양전지의 가격을 저가화할 수가 있다. 이 논문은 점액 상태의 인을 희석시켜서 접촉 홈에 확산공정을 마친 후, 그 기본 특성을 조사하였다. 점액상태점의 희석도와 스핀속도가 산화막의 두께에 영향을 미치는 것이 확인되었다. 희석도가 높을수록 산화막은 두꺼워지고 균일도는 낮아졌다. 희석도 60%의 인이 홈에서의 균일도와 깊이를 고려할 때 가장 적당한 것으로 사료된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.326-329
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• 2002

In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.985-988
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• 2004

The carrier lifetime of boron doped Cz silicon samples after light induced degradation could be improved by optimized rapid thermal processing (RTP). The important five different parameters varied in order to investigate which parameter is important for the stable lifetime after light induced degradation, $\tau_d$. The Plateau temperature and the Plateau time influenced on the lifetime after light induced degradation. Especially, the Plateau temperature showed a strong influence on the stable lifetime. The optimal plateau temperature is approximately $900^{\circ}C$ t for a plateau time of 120 s. The stable lifetime increased from $15\mu}s$ to $25.5{\mu}s$. The normalized defect concentration, $N_t^*$, decreased from $0.06{\mu}s^{-1}$ to $0.037{\mu}s^{-1}$ by RTP-process.

• 한국전기전자재료학회논문지
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• 제20권5호
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.93-96
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• 2002

In this study, PZT thin films were fabricated using sol-gel processing onto Si/$SiO_2$/Ti/Pt substrates. PZT sol with different Zr/Ti ratio(20/80, 30/70, 40/60, 52/48) were prepared, respectively. The films were fabricated by using the spin-coating method on substrates. The films were heat treated at $450^{\circ}C$, $650^{\circ}C$ by rapid thermal annealing(RTA). The preferred orientation of the PZT thin films were observed by X-ray diffraction(XRD), and Scanning electron microscopy(SEM). All of the resulting PZT thin films were crystallized with perovskite phase. The fine crystallinity of the films were fabricated. Also, we found that the ferroelectric properties from the dielectric constant of the PZT thin films were over 600 degrees, P-E hysteresis constant. And the leakage current densities of films were lower than $10^{-8}A/cm^2$. It is concluded that the PZT thin films by sol-gel process to be convinced of application for ferroelectric memory device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.3-4
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• 2005

Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

• 한국재료학회지
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• 제14권12호
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• pp.846-850
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• 2004

NiCo silicide films have been fabricated from $300{\AA}-thick\;Ni_{1-x}Co_{x}(x=0.1\sim0.9)$ on Si-substrates by varying RTA(rapid thermal annealing) temperatures from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 sec. Sheet resistance, cross-sectional microstructure, and chemical composition evolution were measured by a four point probe, a transmission electron microscope(TEM), and an Auger depth profilemeter, respectively. For silicides of the all composition and temperatures except for $80\%$ of the Ni composition, we observed small sheet resistance of sub- $7\;{\Omega}/sq.,$ which was stable even at $1100^{\circ}C$. We report that our newly proposed NiCo silicides may obtain sub 50 nm-thick films by tunning the nickel composition and silicidation temperature. New NiCo silicides from NiCo-alloys may be more appropriate for sub-0.1${\mu}m$ CMOS process, compared to conventional single phase or stacked composit silicides.

• 한국재료학회지
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• 제13권2호
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• pp.88-93
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• 2003

Co/Ti bilayer structure in Co salicide process helps to the improvement of device speed by lowering contact resistance due to the epitaxial growth of $CoSi_2$layers. We investigated the epitaxial growth and interfacial mass transport of $CoSi_2$layers formed from $150 \AA$-Co/Ti structure with two step rapid thermal annealing (RTA). The thicknesses of Ti layers were varied from 20 $\AA$ to 100 $\AA$. After we confirmed the appropriate deposition of Ti film even below $100\AA$-thick, we investigated the cross sectional microstructure, surface roughness, eptiaxial growth, and mass transportation of$ CoSi_2$films formed from various Ti thickness with a cross sectional transmission electron microscopy XTEM), scanning probe microscopy (SPM), X-ray diffractometery (XRD), and Auger electron depth profiling, respectively. We found that all Ti interlayer led to$ CoSi_2$epitaxial growth, while $20 \AA$-thick Ti caused imperfect epitaxy. Ti interlayer also caused Co-Ti-Si compounds on top of $CoSi_2$, which were very hard to remove selectively. Our result implied that we need to employ appropriate Ti thickness to enhance the epitaxial growth as well as to lessen Co-Ti-Si compound formation.