• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.13-14
• /
• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show 61.02% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 46.1% cell area reduction.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.6C
• /
• pp.450-456
• /
• 2005

In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top, and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.4A
• /
• pp.546-552
• /
• 2000

The decoding of Turbo-Code relies on the application of a soft input/soft output decoders which can be realized using maximum-a-posteriori(MAP) symbol estimator[l]. Radix-2 MAP decoder can not be used for high speed communications because of a large number of interleaver block size N. This paper proposed a new simple method for radix-4 MAP decoder based on radix-2 MAP decoder in order to reduce the interleave block size. A branch metrics, forward and backward recursive functions are proposed for applying to radix-4 MAP structure with symbol interleaver. Radix-4 MAP decoder shall be illustratively described and its error performance capability shall be compared to conventional radix-2 MAP decoder in AWGN channel.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.43 no.1 s.307
• /
• pp.101-108
• /
• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show $61.02\%$ cell area reduction comparison with those of the conventional multiplier butterfly structure. furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show $46.1\%$ cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.5
• /
• pp.731-737
• /
• 2000

In this paper we propose a decoding algorithm of Ungerboeck TCM/PSK in the concept of Radix-trellis, which has been applied to the decoding of convolutional codes for the high speed decoding. As an example we choose 16-state trellis coded 8-ary PSK. For Radix-4 and Radix-16 trellis decoding, we explain the path metric(PM) and the branch metric(BM) calculation. By using the simulation, we evaluate the bit error rate(BER) performance according to the number of binary digits for I-Q value, PM and BM registers. The proper number of binary digits of each register has been derived.

• ETRI Journal
• /
• v.32 no.1
• /
• pp.1-10
• /
• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• Journal of IKEEE
• /
• v.25 no.4
• /
• pp.697-702
• /
• 2021

Fast Fourier Transform (FFT) is a major signal processing block being widely used. For long-point FFT processing, usually more than 1024 points, its low-complexity implementation becomes very important while retaining high SQNR (Signal-to-Quantization Noise Ratio). In this paper, we present a low-complexity FFT algorithm with a simple dynamic scaling scheme. For the 2048-point pipelined FFT processing, we can reduce the number of general multipliers by half compared to the well-known radix-2 algorithm. Also, the table size for twiddle factors is reduced to 35% and 53% compared to the radix-2 and radix-2² algorithms respectively, while achieving SQNR of more than 55dB without increasing the internal wordlength progressively.

• Journal of Digital Convergence
• /
• v.11 no.2
• /
• pp.287-297
• /
• 2013

In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The FFT processor is based on radix-8 FFT algorithm and also supports radix-4 or radix-2 FFT computation. We are using efficient "In-place" memory access method to maintain conflict-free data access and minimize memory size. Also we replace a very large lookup table with a twiddle factor generator which consumes less area then a ROM-based lookup table. The proposed FFT processor performs variable-length FFT including 64, 256, 512, 1024, 2048, 4096 and 8192 points which cover all the required FFT lengths used in 802.11a, 802.16a, DAB, DVB-T, VDSL and ADSL.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.1
• /
• pp.683-690
• /
• 2015

Two basic FFT(Fast Fourier Transform) algorithms are the DIT(Decimation-In-Time) and the DIF (Decimation-In-Frequency). In spite of the advantage of the DIT algorithm is to generate a sequential output, various structures have not been made. In this paper, a new DIT Radix-4 FFT butterfly structure are proposed and implemented using Verilog coding. Through synthesis, it is shown that the 64-point FFT is implemented by 6.78 million gates. Since the proposed FFT structure has the advantage of a sequential output, it can be used in OFDM communication SoC(System on a Chip) which need a high speed FFT output.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.6
• /
• pp.1212-1217
• /
• 2004

The main back-bone operation in elliptic curve cryptosystems is scalar point multiplication. The most frequently used method implementing the scalar point multiplication, which is performed in the upper level of GF multiplication and GF division, has been the double-and-add algorithm, which is recently challenged by NAF(Non-Adjacent Format) algorithm. In this paper, we propose a more efficient and novel scalar multiplication method than existing double-and-add by applying redundant receding which originates from radix-4 Booth's algorithm. After deriving the novel quad-and-add algorithm, we created a new operation, named point quadruple, and verified with real application calculation to utilize it. Derived numerical expressions were verified using both C programs and HDL (Hardware Description Language) in real applications. Proposed method of elliptic curve scalar point multiplication can be utilized in many elliptic curve security applications for handling efficient and fast calculations.