• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.31-33
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• 2001

전통적으로 스캔 설계 법칙 검사는 게이트 레벨에서 수행되었다. 그러나 RTL 설계와 합성 도구의 사용이 일반화되면서 게이트 레벨 회로의 검사는 합성 단계에서의 최적화와 스캔 설계 법칙 위배를 정정한 후의 최적화가 필요하여 많은 시간이 소요된다. RTL에서의 스캔 설계 법칙 검사는 이러한 문제를 해결할 수 있으며, 이것이 본 논문의 주제이다. 본 논문에서는 스캔 설계 법칙의 위배를 RTL 설계에서 검사할 수 있는 기법을 제안한다. 이 기법은 효과적인 설계 과정에 의해 설계 시간 을 단축할 수 있을 것이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.78-85
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• 2008

This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the poject with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.

• Journal of the Korea Society for Simulation
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• v.10 no.3
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• pp.15-30
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• 2001

Hybrid simulation may employ different types of simulation based on which models in different system types are developed. The simulation requires simulation time synchronization and data exchange between such simulators, which is called simulators interoperation. This paper develops such interoperable simulation environments for modeling and simulation of hybrid systems whose components consist of continuous and discrete event systems. The environments, one for centerized and the other for distribute, support interoperation between a discrete event simulator of DEVSim++ and a continuous simulator of MATLAB. The centerized environment, HDEVSim++, is developed by extending the sxisting DEVSim++ environment; the distributed environment, HDEVSimHLA, is developed using the HLA/RTl library. Verification of both environments is made and performance comparison between the two using a simple example is presented. .

• The Magazine of the IEIE
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• v.30 no.9
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• pp.1002-1011
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• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• The Journal of the Acoustical Society of Korea
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• v.40 no.3
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• pp.213-218
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• 2021

It is known that total least-squares method shows better estimation performance than least-squares method when noise is present at the input and output at the same time. When total least squares method is applied to data with time series characteristics, Recursive Total Least Squares (RTS) algorithm has been proposed to improve the real-time performance. However, RTLS has numerical instability in calculating the inverse matrix. In this paper, we propose an algorithm for reducing numerical instability as well as having similar convergence to RTLS. For this algorithm, we propose a new RTLS using Iterative Wiener Filter (IWF). Through the simulation, it is shown that the convergence of the proposed algorithm is similar to that of the RTLS, and the numerical robustness is superior to the RTLS.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.246-251
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• 2006

In this paper, we introduce an implementation method of the CBS (Cycle Base Simulator), which describes the operation of a DSP (Digital Signal Processor) at a pipeline cycle level. The CBS is coded with C++, and is verified by comparing the results from the CBS and HDL simulation of the DSP with the various test vectors and application programs. The CBS shows the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The developed CBS can be used in evaluating the performance of the target DSP before the RTL(Register Transfer Level) coding as well as a reference for the RTL level design.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.363-366
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• 2007

This paper evaluated the performance of circuit for compensate the frequency offset in OFDM using Simulink and designed a System Generator model for FPGA implementation. System Generator Model generated HDL code and RTL schematic. Also, evaluate the performance through Hardware Co-simulation, and investigated the result of timing analysis and resource estimation.

• International Journal of Aeronautical and Space Sciences
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• v.18 no.4
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• pp.675-687
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• 2017

In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• Journal of Broadcast Engineering
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• v.18 no.6
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• pp.927-934
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• 2013

This paper aims to realize a Signal to Noise Ratio Estimator which constitutes a critical index of the broadcasting system in OFDM system with a synchronized type based on ISDB-T system. Of the elements which are comprising OFDM segments of ISDB-T system using the MSE algorithm suitable for ASIC design owing to its low complexity among a diverse SNR estimation methods, SNR estimation method using the broadcasting information data and the SNR estimation method using scattered pilot signal were realized by RTL. These two methods were compared in terms of their performance through simulation test not only in the AWGN channel which is an ideal channel, but also in SFN channel and frequency selective fading channel, which are distorted channels. Complexity of two methods were also compared through RTL realization. As a result of this comparison analysis, it was concluded that the SNR estimation method using scattered pilot signal shows more excellent performance and easiness in realization.