• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.35-44
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• 2002

In this paper, an implementation method of RSA exponentiator based on Radix-$2^k$ modular multiplication algorithm is presented and verified. We use Booth receding algorithm to implement Radix-$2^k$ modular multiplication and implement radix-16 modular multiplier using 2K-byte memory and CSA(carry-save adder) array - with two full adder and three half adder delays. For high speed final addition we use a reduced carry generation and propagation scheme called pseudo carry look-ahead adder. Furthermore, the optimum value of the radix is presented through the trade-off between the operating frequency and the throughput for given Silicon technology. We have verified 1,024-bit RSA processor using Altera FPGA EP2K1500E device and Samsung 0.3$\mu\textrm{m}$ technology. In case of the radix-16 modular multiplication algorithm, (n+4+1)/4 clock cycles are needed and the 1,024-bit modular exponentiation is performed in 5.38ms at 50MHz.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.285-288
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• 2002

In this paper, a new structure of 1024-bit high-speed RSA cryptosystem has been proposed and implemented in hardware to increase the operation speed and enhance the variable-length operation in the plain text. The proposed algorithm applied a radix-4 Booth algorithm and CSA(Carry Save Adder) to the Montgomery algorithm for modular multiplication As the results from implementation, the clock period was approached to one delay of a full adder and the operation speed was 150MHz. The total amount of hardware was about 195k gates. The cryptosystem operates as the effective length of the inputted modulus number, which makes variable length encryption rather than the fixed-length one. Therefore, a high-speed variable-length RSA cryptosystem could be implemented.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1551-1554
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• 2002

In this paper, the hardware implementation of the RSA public-key cryptographic algorithm is presented. The RSA cryptographic algorithm is depends on the computation of repeated modular exponentials. The Montgomery algorithm is used and modified to reduce hardware resources and to achieve reasonable operating speed for smart card. An efficient architecture for modular multiplications based on the array multiplier is proposed. We have implemented a 10240it RSA cryptographic processor based on proposed scheme in IESA system developed for smart card emulating system. As a result, it is shown that proposed architecture contributes to small area and reasonable speed for smart cards.

• International Journal of Computer Science & Network Security
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• v.24 no.1
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• pp.196-204
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• 2024

The security of data and information using encryption algorithms is becoming increasingly important in today's world of digital data transmission over unsecured wired and wireless communication channels. Hybrid encryption techniques combine both symmetric and asymmetric encryption methods and provide more security than public or private key encryption models. Currently, there are many techniques on the market that use a combination of cryptographic algorithms and claim to provide higher data security. Many hybrid algorithms have failed to satisfy customers in securing data and cannot prevent all types of security threats. To improve the security of digital data, it is essential to develop novel and resilient security systems as it is inevitable in the digital era. The proposed hybrid algorithm is a combination of the well-known RSA algorithm and a simple symmetric key (SSK) algorithm. The aim of this study is to develop a better encryption method using RSA and a newly proposed symmetric SSK algorithm. We believe that the proposed hybrid cryptographic algorithm provides more security and privacy.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.157-162
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• 2010

Due to the IT development, RFID/USN became very familiar means of communication. However, because of increased number, security, and size constraints of nodes, it is insufficient to implement a variety of services. To solve these problems, this paper suggests RI-RSA, which is an appropriate asymmetric cryptographic system for RFID/USN environment. The proposed RI-RSA cryptographic system is easy to implement. To increase the processing speed, RI-RSA was suggested by subdividing the multiplication section into two-dimensional, where bottleneck phenomena occurs, and it was implemented in the hardware chip level. The simulation result verified that it caused 6% of circuit reduction, and for the processing speed, RI-RSA was 30% faster compare to the existing RSA.

• Journal of Service Research and Studies
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• v.5 no.2
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• pp.71-81
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• 2015

The RSA public key encryption algorithm, a few, key generation, factoring, the Euler function, key setup, a joint expression law, the application process are serial indexes. The foundation of such algorithms are mathematical principles. The first concept from mathematics principle is applied from how to obtain a minority. It is to obtain a product of two very large prime numbers, but readily tracking station the original two prime number, the product are used in a very hard principles. If a very large prime numbers p and q to obtain, then the product is the two $n=p{\times}q$ easy station, a method for tracking the number of p and q from n synthesis and it is substantially impossible. The RSA encryption algorithm, the number of digits in order to implement the inverse calculation is difficult mathematical one-way function and uses the integer factorization problem of a large amount. Factoring the concept of the calculation of the mod is difficult to use in addition to the problem in the reverse direction. But the interests of the encryption algorithm implementation usually are focused on introducing the film the first time you use encryption algorithm but we have to know how to go through some process applied to the field work This study presents a field force applied encryption process scheme based on public key algorithms attribute diagnosis.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 2003.11a
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• pp.111-118
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• 2003

Java Card API written to optimize Execute Environment in embedded device of small memory such as smart card. Java Card API intended to provide many advance when develope smart card based program. this paper purpose to implement RSA Algorithm of public key Algorithms with Java Card API.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.3-11
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• 2000

In this paper, we design modular multiplication systolic array and exponentiation processor having n bits message black. This processor uses Montgomery algorithm and LR binary square and multiply algorithm. This processor consists of 3 divisions, which are control unit that controls computation sequence, 5 shift registers that save input and output values, and modular exponentiation unit. To verify the designed exponetion processor, we model and simulate it using VHDL and MAX+PLUS II. Consider a message block length of n=512, the time needed for encrypting or decrypting such a block is 59.5ms. This modular exponentiation unit is used to RSA cryptosystem.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10b
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• pp.843-846
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• 2001

SET보안 프로토콜은 DES, RSA, Hash 알고리즘으로 구성되어있는데, 본 연구는 기존의SET에서 사용되는 RSA알고리즘대신에 ECC알고리즘을 연구 개발하였고, 이것을 RSA와 속도면에서 성능을 비교 분석 하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1093-1100
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• 2015

Since the security of RSA cryptosystem depends on the difficulty of factoring integers, it is the most important problem to factor large integers in RSA cryptosystem. The Lenstra elliptic curve factorization method(ECM) is considered a special purpose factoring algorithm as it is still the best algorithm for divisors not greatly exceeding 20 to 25 digits(64 to 83 bits or so). ECM, however, wastes most time to calculate $M{\cdot}P$ mod N and so Montgomery and Koyama both give fast methods for implementing $M{\cdot}P$ mod N. We, in this paper, further analyze Montgomery and Koyama's methods and propose an efficient algorithm which choose the optimal parameters and reduces the number of multiplications of Montgomery and Koyama's methods. Consequently, the run time of our algorithm is reduced by 20% or so than that of Montgomery and Koyama's methods.