• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.96-103
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• 2008

This paper proposes a new low-power and small-area Reed-Solomon decoder. The proposed Reed-Solomon decoder using a novel simplified form of the modified Euclid's algorithm can support low-hardware complexity and low-Power consumption for Reed-Solomon decoding. The simplified modified Euclid's algorithm uses new initial conditions and polynomial computations to reduce hardware complexity, and thus, the implemented architecture consisting of 3r basic cells has the lowest hardware complexity compared with existing modified Euclid's and Berlekamp-Massey architectures. The Reed-Solomon decoder has been synthesized using the $0.18{\mu}m$ Samsung standard cell library and operates at 370MHz and its data rate supports up to 2.9Gbps. For the (255, 239, 8) RS code, the gate counts of the simplified modified Euclid's architecture and the whole decoder excluding FIFO memory are only 20,166 and 40,136, respectively. Therefore, the proposed decoder can reduce the total gate count at least 5% compared with the conventional DCME decoder.

• Journal of the Korea Society of Computer and Information
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• v.15 no.4
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• pp.83-90
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• 2010

In wireless sensor networks, the data transmitted from the sensor nodes are susceptible to corruption by errors which caused of noisy channels and other factors. In view of the severe energy constraint in Sensor Networks, it is important to use the error control scheme of the energy efficiently. In this paper, we presented RS (Reed-Solomon) codes in terms of their BER performance and power consumption. RS codes work by adding extra redundancy to the data. The encoded data can be stored or transmitted. It could have errors introduced, when the encoded data is recovered. The added redundancy allows a decoder to detect which parts of the received data is corrupted, and corrects them. The number of errors which are able to be corrected by RS code can determine by added redundancy. The results of experiment validate the performance of proposed method to provide high degree of reliability in low-power communication. We could predict the lifetime of RS codes which transmitted at 32 byte a 1 minutes. RS(15, 13), RS(31, 27), RS(63, 57), RS(127,115), and RS(255,239) can keep the days of 173.7, 169.1, 163.9, 150.7, and 149.7 respectively. The evaluation based on packet reception ratio (PRR) indicates that the RS(255,239) extends a sensor node's communication range by up about 3 miters.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.37-43
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• 1999

Two-way addressing method has been proposed for efficient VLSI implementation of Euclidean calculation circuit for pipelined Reed-Solomon decoder. This new circuit is operating with single clock while exploiting maximum parallelism, and uses register addressing instead of register shifting to minimize the switching power. Logic synthesis shows the circuit with the new scheme takes 3,000 logic gates, which is about 40% reduction from the previous 5,000 gate implementation. Computer simulation also shows the power consumption is about 3mW. The previous implementation with multiple clock consumed about 5mW.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.5
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• pp.15-20
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• 2012

In this paper, we show new method to find the error locations of received Reed-Solomon code word. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square/$X^4$ calculating circuit, parallel processing and not using the very complex Divider. The Reed Solomon decoder using this new Chien Machine can be applicated for data protection of almost all digital communication and consumer electronic devices.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.306-312
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• 2000

In this paper, the efficient architecture of small Reed-solomon architecture is suggested. Here, 3-stage pipeline is adopted. In decoding, error-location polynomials are obtained by BMA using fast iteration method, and syndrome polynomials, where calculation complexity is required, are obtained by parallel calculation using ROM table, and the roots of error location polynomial are calculated by ROM table using Chein search algorithm. In the suggested decoder, it is confirmed that 3 symbol random errors can be corrected and 124Mbps decoding rate is obtained using 25 Mhz system clock.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2004.11a
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• pp.103-106
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• 2004

본 논문에서는 PC 기반 지상파 DMB(Terrestrial Digital Multimedia Broadcasting, T-DMB) 수신기를 위한 SW 최적화에 대해 설명한다. 이 수신기는 PC 외부에 지상파 DMB 신호를 안테나로 수신하여 복조하고 채널 복호하는 프론트 엔드(front-end) 수신 모듈을 이용, USB를 통하여 RS(Reed-Solomon) 부호화된 MPEG-2 TS(Transport Stream) 데이터를 읽어 들여 RS 복호, TS 역다중화, 비디오 복호, 오디오 복호 등의 SW 처리 과정을 거쳐 디스플레이 상에 수신 내용을 표시하게 된다. 본 논문에서는 저사양 PC에서도 T-DMB를 수신할 수 있도록 H.264/MPEG-4 AVC(Advanced Video Coding) 복호 과정을 최적화한 결과에 대해 설명한다.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3212-3214
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• 1999

RS(Reed-Solomon)부호는 오류 정정을 위한 채널 코딩기법중의 하나로 특히 연집 오류에 대해 강한 특성을 갖고 있으며, CD-P(Compact Disc Player), DAT(Digital Audio Tape). VTR, DVD(Digital Video Disc), 디지탈 TV 디코더등에서 사용되고 있다. 본 논문은 Galois Field, GF[$2^8$]상에서 (204. 188. 8)의 규격을 갖는 디지탈 TV용 RS 복호기의 구현에 관한 연구로 8개의 심볼 오류까지 정정 가능하다. 오증 계산은 16개의 오증 계산셀로 구성되어 지며, 오류 위치 다항식을 계산하는데 있어서는 Berlekamp-Massey 알고리즘을 사용한다. VHDL로 설계되어 Synopsys를 이용하여 검증 및 합성하였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.53-56
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• 2010

본 논문은 Shannon의 정리에 따른 채널 용량에 근접한 성능을 보이는 것으로 알려진 터보 복호기 기반의 반복적인 검출과 복호화(Iterative Detection and Decoding) 기법에서 반복적인 복호화를 수행할 시에 제외되었던 리스트 구 복호기(List Sphere Decoder)에서 사전 정보(prior information)을 이용할 수 있도록 하여 수정된 IDD 기법을 제안하였다. 기존의 기법에서는 사후확률(A posteriori probability)을 계산하기 위하여 리스트 구 복호기를 사용하였으나 반복적인 복호화 수행 시에는 사전 정보를 이용하지 않는 특성으로 인하여 제외된다. 만약 잡음(noise) 등의 이유로 검출된 심볼 벡터 목록이 원래의 것과 매우 다른 경우라도 재 검출을 하지 않기 때문에 반복적인 복호화를 수행하더라도 원래의 정보에 근접하기 어렵게 된다. 본 논문에서는 이러한 기존의 기법에서 리스트 구 복호기를 터보 복호기의 Log Likelihood Ratio (LLR) 값을 사전 정보로 이용할 수 있도록 수정된 리스트 구 복호기를 제안하였다. 수정된 리스트 복호기는 반복적인 복호화를 수행 시 이전의 복호화에서 얻은 정보를 이용하여 새로이 검출된 심볼 벡터 목록을 제공하게 된다. 실제의 통신환경과 유사한 모델의 실험을 통해 수정된 IDD 기법이 기존의 IDD로 구성되는 내부 피드백에 RS 복호기 기반의 외부 피드백으로 구성된 형태로 피드백 회수가 증가할수록 기존의 IDD에 비해 성능이 개선됨을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.552-555
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• 2010

In this paper, we propose a context-aware system using wireless multi sensor module to monitor the state for industrial factory environment. Wireless multi sensor module combines sensing values which are collected from each acceleration, pressure, temperature and gas sensors. Moreover, it delivers this data to server after being encoded by RS code. Thereafter, RS decoder decodes the values that are received from wireless multi sensor module and fixes errors which occur in wireless communication. Based on decoded data, context-aware algorithm sets critical range and compares it to the sensing values, if the sensing values are out of the range, an event occurs by the algorithm. At the same time, if there is another sensing value which is out of the range for standby time T seconds, the algorithm orders 3 steps-alarm to occur depending on each situation. Through this system, it becomes eventually possible to monitor machines' condition effectively. From the simulation, we confirm that this system is efficient to status monitoring of industrial automation equipment.