• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.1957-1959
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• 2005

표면이 도핑된 SOI RESURF LDMOSFET에 대해 표면 도핑의 깊이에 따른 항복전압 및 순방향 특성을 분석하였다. 표면 도핑영역의 깊이를 $0.5{\sim}2.0{\mu}m$까지 변화시켜가며 항복전압의 변화와 온-저항의 변화를 시뮬레이션 하였다. 표면 도핑영역의 깊이에 따라 항복전압은 $73V{\sim}138V$까지 변화하였으며, 온-저항도 $0.18{\sim}0.143{\Omega}/cm^2$까지 변화하였다. 항복전압은 표면 도핑 영역의 깊이가 $1.5{\mu}m$때 138V로 가장 높게 나타났으며, 동일한 에피 영역의 농도를 사용한 기존의 소자와 비교하였을 때 약 22.1%의 항복전압의 증가를 나타냈으며, 온-저항값은 약 21.8%정도 감소하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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• pp.156-158
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• 2002

Reduction of on-resistance($R_{on}$) in high voltage devices is of critical importance for the power consumption of the device. $R_{on}$ decreases with increase of the doping concentration of the drift region. However, breakdown voltage(BV) decreaes also with increase of doping concentration. In this report, a multi-resurf LDMOS[1] strcuture is proposed to reduce the $R_{on}$ which allows no degradation in BV. The on-and off-state characteristics of the proposed structure are simulated using the two-dimensional devices simulator ATLAS and compared with those from the conventional structure.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.101-102
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• 2005

SiC lateral power semiconductor device has high breakdown voltage and low on-state voltage drop due to the material characteristics. And, because the high breakdown voltage can be obtained, RESURF technique is mostly used in silicon power semiconductor devices. In this paper, we presents the electrical characteristics of the 4H-SiC RESURF LDMOSFET as a function of the epi-layer length, concentration and thickness. 240~780V of breakdown voltage can be obtained as a function of epi-layer length and thickness with same epi-layer concentration.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.355-358
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• 2004

In this work, N-LDMOSFET(Lateral Double diffused MOSFET) was designed and fabricated on SOI(Silicon-On-Insulator) substrate, for such applications as motor controllers and high voltage switches, fuel injection controller systems in automobile and SSR(Solid State Rexay)etc. The LDMOSFET was designed to overcome the floating body effects that appear in the conventional thick SOI MOS structure by adding p+ region in source region. Also, RESURF(Reduced SURface Field) structure was proposed in this work in order to reduce a large on-resistance of LDMOSFET when operated keeping high break down voltage. Breakdown voltage was 268v in off-state ($V_{GS}$=OV) at room temperature in $22{\mu}m$ drift length LDMOSFET. When 5V of $V_{GS}$ and 30V of $V_{DS}$ applied, the on resistance(Ron), the transcon ductance($G_m$) and the threshold voltage($V_T$) was 1.76k$\Omega$, 79.7uA/V and 1.85V respectively.

• 전자공학회논문지D
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• 제35D권8호
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• pp.38-43
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• 1998

An analytical model for the surface field distribution of the RESURF (reduced surface field)LD(lateral double-diffused) MOS is presented in terms of the doping concentration, the thickness of the n epi layer, the p substrate concentration, and the epi layer length. The reuslts are used to determine the breakdown voltage due to the surface field as a function of the epi layer length. The maximum breakdown voltage of the device is found to be that of the vertical n$^{+}$n$^{[-10]}$ p$^{[-10]}$ junction. Analytical results of the breakdown voltage vs. the epi layer length agree well with the numerical simulation results using MEDICI.I.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.365-368
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• 2004

Charge compensation effects in multi-resurf structure make possible to obtain high breakdown volatage and low on-resistance in vertical MOSFET. In this paper, electrical characteristics of the vertical MOSFET with multi epitaxial layer is presented. Proposed device has n and p-pillar for obtaining the charge compensation effects and The doping concentration each pillar is varied from $5{\times}10^{14}\;to\;1{\times}10^{16}/cm^3$. The thickness of the proposed device also varied from $400{\mu}m\;to\;500{\mu}m$. Due to the charge compensation effects, 4500V of breakdown voltage can be obtained.

• ETRI Journal
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• 제20권1호
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• pp.37-45
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• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1579-1581
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• 1996

The high temperature characteristics of SOI BMFET are analyzed by the numerical simulation and compared with MOS-gated SOI power devices at high temperatures. The proposed SOI BMFET combines bipolar operation in the on-state with unipolar FET operation in the off-state, so that it may be suitable for high temperature operation without any significant degradation of performance such as the leakage current and blocking capability. The simulation results show that SOI BMFET with a higher doped n-resurf layer is the most promising device far high temperature application as compared with MOS-gated SOI power devices, exhibiting the low on-state voltage drop as well as the excellent forward blocking capability at high temperature.

• ETRI Journal
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• 제34권6호
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• pp.962-965
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• 2012

In this letter, we propose a new RESURF stepped oxide (RSO) process to make a semi-superjunction (semi-SJ) trench double-diffused MOSFET (TDMOS). In this new process, the thick single insulation layer ($SiO_2$) of a conventional device is replaced by a multilayered insulator ($SiO_2/SiN_x/TEOS$) to improve the process and electrical properties. To compare the electrical properties of the conventional RSO TDMOS to those of the proposed TDMOS, that is, the nitride_RSO TDMOS, simulation studies are performed using a TCAD simulator. The nitride_RSO TDMOS has superior properties compared to those of the RSO TDMOS, in terms of drain current and on-resistance, owing to a high nitride permittivity. Moreover, variations in the electrical properties of the nitride_RSO TDMOS are investigated using various devices, pitch sizes, and thicknesses of the insulator. Along with an increase of the device pitch size and the thickness of the insulator, the breakdown voltage slowly improves due to a vertical field plate effect; however, the drain current and on-resistance degenerate, owing to a shrinking of the drift width. The nitride_RSO TDMOS is successfully fabricated, and the blocking voltage and specific on-resistance are 108 V and $1.1m{\Omega}cm^2$, respectively.

• 전기전자학회논문지
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• 제15권1호
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• pp.37-42
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• 2011

본 논문에서는 0.35 um BCD 공정을 통한 고내압 BCD 소자와 새로운 구조의 BCD 소자를 제작하여 전기적 특성을 분석하였다. 20 V급 BJT 소자, 30/60 V급 HV-CMOS, 40/60 V급 LDMOS 소자의 전기적 특성을 분석하고, 동일 공정을 통해 높은 전류 이득을 갖는 수직/수평형 NPN BJT와 고내압 특성의 LIGBT 소자를 제안하였다. 제안된 수직/수평형 NPN BJT의 항복전압은 15 V, 전류이득은 100으로 측정되었으며, 고내압 특성의 LIGBT의 항복전압은 195 V, 문턱전압은 1.5 V, Vce,sat은 1.65 V로 측정 되었다.