• 정보보호학회논문지
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• 제27권3호
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• pp.449-457
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• 2017

본 논문에서는 양자난수발생기 Quantis의 후처리 과정에 대하여 암호학의 관점에서 실험을 통하여 안전성과 성능을 분석하였다. Quantis의 후처리 과정은 수학적 이론에 근거한 이진행렬-벡터 곱 연산을 통해 풀엔트로피(full-entropy)를 출력하도록 설계되었고, NIST SP 800-90B의 최소엔트로피(min-entropy) 추정 테스트를 이용하여 이를 검증하였다. 이진행렬-벡터 곱 연산에 최적화 기법을 사용함으로써 난수 생성 속도에 미치는 영향을 최소화하였음을 확인하고, NIST SP 800-90B에서 제시한 검증된 Conditioning과의 난수 출력 성능을 비교하였다. 또한, 미국 NIST와 독일 BSI의 난수발생기 표준 모델과 Quantis의 부합되는 요소와 아닌 요소를 구분하였다. Quantis를 암호학의 용도로 사용하고자할 경우, CMVP 기준에 적합하게 이용하기 위해 Quantis의 출력 데이터를 승인된 의사 난수발생기의 씨드로 사용하여 출력한 난수를 사용하는 것이 적절하다고 판단된다.

• ETRI Journal
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• 제45권3호
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• pp.365-378
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• 2023

ARIA is a block cipher proposed by Kwon et al. at ICISC 2003 that is widely used as the national standard block cipher in the Republic of Korea. Herein, we identify some flaws in the quantum rebound attack on seven-round ARIA-DM proposed by Dou et al. and reveal that the limit of this attack is up to five rounds. Our revised attack applies to not only ARIA-DM but also ARIA-MMO and ARIA-MP among the PGV models, and it is valid for all ARIA key lengths. Furthermore, we present dedicated quantum rebound attacks on seven-round ARIA-Hirose and ARIA-MJH for the first time. These attacks are only valid for the 256-bit key length of ARIA because they are constructed using the degrees of freedom in the key schedule. All our attacks are faster than the generic quantum attack in the cost metric of the time-space tradeoff.

• ETRI Journal
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• 제45권3호
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• pp.534-542
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• 2023

The large amount of secondary effects in complementary metal-oxide-semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2003년도 High Temperature Superconductivity Vol.XIII
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• pp.53-53
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• 2003

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2005년도 High Temperature Superconductivity Vol.XV
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• pp.46-46
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• 2005

• Progress in Superconductivity
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• 제8권2호
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• pp.181-185
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• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.

• 정보보호학회논문지
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• 제28권1호
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• pp.73-83
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• 2018

미래의 양자 컴퓨팅 환경에 대응한 양자내성 암호 알고리즘의 연구 개발이 NIST를 비롯한 국내외 연구기관 및 기업들의 참여 하에 활발히 이루어지고 있다. 양자내성 암호 알고리즘으로는 다변수다항식-기반, 부호-기반, 격자-기반, 해시-기반, 그리고 아이소제니-기반 암호 알고리즘들이 연구되고 있다. 그 중에서 아이소제니-기반(isogeny-based) 암호 알고리즘은 가장 최근에 등장했으며 타원곡선 연산을 사용하고, 양자내성 암호 알고리즘들 중 가장 짧은 키 길이를 가지고 있어 주목받고 있다. 본 논문에서는 초특이 아이소제니 Diffie-Hellman (SIDH) 프로토콜을 저사양 모바일 환경에 적합하도록 파라미터를 선택하고 효율적으로 구현하였다. 파라미터로는 현재의 보안강도와 저사양 모바일 환경을 고려하여 523비트 소수 유한체 상에서 정의되는 초특이 타원곡선을 선택하였으며 그에 최적화된 아이소제니 계산 전략 트리를 생성하였다. 적용 SIDH 모듈은 32비트 환경에서 동작하도록 구현하였다.

• Progress in Superconductivity
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• 제5권1호
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.902-905
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• 2004

A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUID) sensors for precision MCG signal acquisitions. Such system is composed of hundreds of sensors, requiring fast signal sampling and precise analog-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit 1ks/s, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 ms speed. The test result shows that the signal acquisition is done in 168 usuc which is much shorter than the required 1 ms period. This hardware will be extended to 256 channel data acquisition to be used for the diagnosis system.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.117-119
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• 2003

We have designed fabricated, and tested an RSFQ(Rapid Single Flux Quantum) 1-bit ALU (Arithmetic Logic Unit). The 1-bit ALU was composed of a half adder and three SFQ DC switches. Three DC switches were attached to the two output ports of an ALU for the selection of each function from the available functions that were AND, OR, XOR and ADD. And we also attached two DC switches at the input ports of the half adder so that the input data were controlled using the function generators operating at low speed while we tested the circuit at high speed. The test bandwidth was from 1KHz to 5 ㎓. The chip was tested at the liquid helium temperature of 4.2 K.