• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.73-83
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• 2007

In this paper, we propose macroblock(MB)-based adaptive interpolation filter method for improving coding efficiency in H.264/AVC. In the proposed method, nine separable two-dimensional(2D) interpolation filters are applied for precisely compensating motions in various directions. The optimal cost function which considers the bit rate and distortion for coding the MB is defined. The filter is adaptively selected per MB for minimizing the defined cost function. In the experimental results, the proposed method shows more excellent in coding efficiency than the conventional methods for the various standard $QCIF(176{\times}144)/CIF(352{\times}288)$ video test sequences. It leads to about 6.25%(1 reference frame) and 3.46%(5 reference frames) bit rate reduction on average compared to the H.264/AVC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.296-306
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• 2003

In this paper, algorithm for non-iterative decoding method is proposed and fractal image decoder based on non-iterative fractal decoding algorithm used general purpose digital signal processors is designed and implemented. The algorithm is showed that the attractor image can be obtained analytically whe n the image is encoded using the fractal algorithm proposed by Monro and Dudbridge, in which the corresponding domain block for a range block is fifed. Using the analytical formulas, we can obtain the attractor image without iteration procedure. And we get general formulas of obtained analytical formulas. Computer simulation results for various test images show that we can increase the image decoding speed by more than five times when we use the analytical formulas compared to the previous iteration methods. The fractal image decoder contains two ADSP2181's and perform image decoding by three stage pipeline structure. The performance tests of the implemented decoder is elapsed 31.2ms/frame decoding speed for QCIF data when all the frames are decoded. The results enable us to process the real-time fractal decoding over 30 frames/sec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1541-1550
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• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1288-1291
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• 2002

In this paper, we present a design of mpeg-4 video codec chip to reduce the power consumption using frame level clock gating and motion estimation skip scheme. It performs 30 grames/s of codec (encoding and decoding) mode with quarter-common intermediate format(QCIF) at 27MHz. A novel low-power techniques were implemented in architectural level, which is 35% of the power dissipation for a conventional CMOS design. This chip performs MPEG-4 Simple Profile Level 2(Simple@L2) and H.263 base mode. Its contains 388,885 gates, 662k bits memory, and the chip size was 9.7 mm x 9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1308-1311
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• 2002

We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in wireless multimedia applications. The discussion will focus on the architectural design techniques for implementing a high-performance video compression/decompression chip at low power architectures. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz for 128k∼144kbps. By introducing the efficiently optimized Frame Memory Interface architecture, low power motion estimation and embedded ARM microprocessor and AMBA interface, the proposed MPEG-4 video codec has low power consumption for wireless multimedia applications such as IMT-2000.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.83-86
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.839-842
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• 2003

본 논문에서는 MPEG-4 디블록킹 필터를 매크로블록 단위의 효율적인 파이프라인 구조를 사용하여 구현하였다. MPEG-4 QCIF/CIF 영상 시퀀스의 디블록킹 필터링 효과를 보일것이며, 디블록킹 필터링의 많은 계산량을 줄임과 동시에 낮은 클록에서 실시간 처리할 수 있는 구조를 제안하였다. 대부분 블록기반의 비디오 코딩 시스템에서, 블록 에지 효과는 블록기반 영상 압축에 치명적인 화질 저하를 나타낸다. 특히 압축 비율이 커질수록 화질 저하는 뚜렷하다. 그래서, 영상 후처리 기술로서 디블록킹 필터를 사용하여 블록 에지 영향을 줄임으로써 영상 화질을 향상시킨다. 그러나 디블록킹 필터의 주요 단점은 많은 계산량을 요구하고 있어서 구현에 어려움이 있다. 이 문제를 해결하기 위해, MPEG-4 디블록킹 필터를 매크로 블록단위의 파이프라인 구조로 설계하였고, 실시간으로 동작하는 MPEG-4 SP@L2의 비디오 코덱 칩을 구현하였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1928-1931
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• 2003

본 논문은 가장 최근의 동영상 국제표준인 H.264 비디오 코덱을 사용하여 QCIF 영상을 초당 10 프레임 정도의 속도로 실시간 부호화하는 것을 목적으로, 부호화 시 필요한 연산의 약 80％-90％를 차지하는 움직임 추정을 고속으로 처리할 수 있는 알고리즘을 개발하는 것을 내용으로 하고 있다. 제안하는 고속 움직임 추정 알고리즘은 MPEG겨 등의 고속 움직임 추정에 사용되었던 기존의 알고리즘을 다중 프레임 레퍼런스 등 새로운 특징을 갖는 H.264 코덱에 적합한 형태로 개선하고, 움직임 추정의 정밀도가 1/4 화소 단위로 향상됨으로써 늘어난 부화소단위 움직임 추정의 상대적 부담을 함께 고려하면서, 모드 선택과정과 효과적으로 결합함으로써 보다 향상된 성능을 나타내고 있다. 모의실험 결과, 기존의 공식 JVT-AVC 레퍼런스 소프트웨어인 JM (Joint Model) 에 구현되어 있는 고속 움직임 추정 알고리즘에 비해서 최대 80％, 평균적으로 60％의 속도개선 효과가 있음이 입증되어, 최근 JM 의 새로운 고속 움직임 추정 알고리즘으로 채택된 JVT-F0l7 알고리즘에 본 논문에서 제안하는 레퍼런스 프레임 탐색 제한 알고리즘을 결합시킴으로써 추가적으로 약 45％의 속도 개선을 얻을 수 있음을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.318-321
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• 2009

We have studied transparent top gate Al-Zn-Sn-O (AZTO) TFTs with an $Al_2O_3$ protective layer (PL) on an active layer. We also fabricated a transparent 2.5 inch QCIF+AMOLED display panel using the AZTO TFT back-plane. The AZTO active layers were deposited by RF magnetron sputtering at room temperature and the PL was deposited by ALD with two different processes. The mobility and subthreshold slope were superior in the cases of the vacuum annealing and the oxygen plasma PL compared to the $O_2$ annealing and the water vapor PL, however, the bias stability was excellent for the TFTs of the $O_2$ annealing and the water vapor PL.