• Proceedings of the Korean Vacuum Society Conference
• /
• 2009.08a
• /
• pp.199-199
• /
• 2009

• Bulletin of the Korean Chemical Society
• /
• v.33 no.9
• /
• pp.2830-2844
• /
• 2012

This review covers recent developments in our group regarding the synthesis, characterization and applications of single-crystalline one-dimensional nanostructures based on a wide range of material systems including noble metals, metal silicides and metal germanides. For the single-crystalline one-dimensional nanostructures growth, we have employed chemical vapor transport approach without using any catalysts, capping reagents, and templates because of its simplicity and wide applicability. Au, Pd, and Pt nanowires are epitaxially grown on various substrates, in which the nanowires grow from seed crystals by the correlations of the geometry and orientation of seed crystals with those of as-grown nanowires. We also present the synthesis of numerous metal silicide and germanide 1D nanostructures. By simply varying reaction conditions, furthermore, nanowires of metastable phase, such as $Fe_5Si_3$ and $Co_3Si$, and composition tuned cobalt silicides (CoSi, $Co_2Si$, $Co_3Si$) and iron germanides ($Fe_{1.3}Ge$ and $Fe_3Ge$) nanowires are synthesized. Such developments can be utilized as advanced platforms or building blocks for a wide range of applications such as plasmonics, sensings, nanoelectronics, and spintronics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.06a
• /
• pp.87-91
• /
• 1998

In this paper, We analyzed the current-voltage characteristics with n-type silicon substrates concentration and temperature variations (Room temperature, 50$^{\circ}C$, 75$^{\circ}C$) in platinum silicide and silicon junction. The electrical parameters of measurement are turn-on voltage, saturation current, ideality factor, barrier height, dynamic resistance in forward bias and reverse breakdown voltage according to variations of junction concentration of substrates and measurement temperature variations. As a result, the forward turn-on voltage, reverse breakdown voltage, barrier height and dynamic resistance were decreased but saturation currents and ideality factor were increased by substrates increased concentration variations in platinum silicide and n-silicon junction. In increased measurement temperature (RT, 50$^{\circ}C$, 75$^{\circ}C$), the extracted electrical parameter values of characteristics were rises by increased temperature variations according to the forward and reverse bias.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.146-146
• /
• 2010

일반적인 MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor)은 소스와 드레인의 형성을 위해서 불순물을 주입하고 고온의 열처리 과정을 거치게 된다. 이러한 고온의 열처리 과정 때문에 녹는점이 낮은 메탈게이트와 게이트 절연막으로의 high-k 물질의 사용에 제한을 받게된다. 이와 같은 문제점을 보완하기 위해서 소스와 드레인 영역에 불순물 주입공정 대신에 금속접합을 이용한 Schottky Barrier Tunnel Transistor (SBTT)가 제안되었다. SBTT는 $500^{\circ}C$ 이하의 저온에서 불순물 도핑없이 소스와 드레인의 형성이 가능하며 실리콘에 비해서 수십~수백배 낮은 면저항을 가지며, 단채널 효과를 효율적으로 제어할 수 있는 장점이 있다. 또한 고온공정에 치명적인 단점을 가지고 있는 high-k 물질의 적용 또한 가능케한다. 본 연구에서는 p-type SOI (Silicon-On-Insulator) 기판을 이용하여 Pt-silicide 소스와 드레인을 형성하고 전기적인 특성을 분석하였다. 또한 본 연구에서는 기존의 sidewall을 사용하지 않는 새로운 구조를 적용하여 메탈게이트의 사용을 최적화하였고 게이트 절연막으로써 실리콘 옥사이드를 스퍼터링을 이용하여 증착하였기 때문에 저온공정을 성공적으로 수행할 수 있었다. 이러한 게이트 절연막은 열적으로 형성시키지 않고도 70 mv/dec 대의 우수한 subthreshold swing 특성을 보이는 것을 확인하였고, $10^8$정도의 높은 on/off current ratio를 갖는 것을 확인하였다.

• Korean Journal of Materials Research
• /
• v.27 no.2
• /
• pp.94-99
• /
• 2017

Dinickel-silicide $(Ni_2Si)/glass$ was employed as a counter electrode for a dye-sensitized solar cell (DSSC) device. $Ni_2Si$ was formed by rapid thermal annealing (RTA) at $700^{\circ}C$ for 15 seconds of a 50 nm-Ni/50 nm-Si/glass structure. For comparison, $Ni_2Si$ on quartz was also prepared through conventional electric furnace annealing (CEA) at $800^{\circ}C$ for 30 minutes. XRD, XPS, and EDS line scanning of TEM were used to confirm the formation of $Ni_2Si$. TEM and CV were employed to confirm the microstructure and catalytic activity. Photovoltaic properties were examined using a solar simulator and potentiostat. XRD, XPS, and EDS line scanning results showed that both CEA and RTA successfully led to tne formation of nano $thick-Ni_2Si$ phase. The catalytic activity of $CEA-Ni_2Si$ and $RTA-Ni_2Si$ with respect to Pt were 68 % and 56 %. Energy conversion efficiencies (ECEs) of DSSCs with $CEA-Ni_2Si$ and $RTA-Ni_2Si$catalysts were 3.66 % and 3.16 %, respectively. Our results imply that nano-thick $Ni_2Si$ may be used to replace Pt as a reduction catalytic layer for a DSSCs. Moreover, we show that nano-thick $Ni_2Si$ can be made available on a low-cost glass substrate via the RTA process.

• Korean Journal of Materials Research
• /
• v.4 no.2
• /
• pp.143-151
• /
• 1994

On PT/Ti/Si substrates, PZT thln fllms are deposited at $300^{\circ}C$ by rf magnetron sputtering uslng a $(PbZr_{52}, Ti_{48})O_{3}$ composltc cerarnlc target. To abtaln, the stable phase, perovskltc structure, furnace annealmg techmque had been cmplo:~d In PbO amb~ent for the $550^{\circ}C$-$750^{\circ}C$ temperature ranges. On Pt(250$\AA$)/Ti(500$\AA$)/Si, Pt(1000)$\AA$/Ti(500$\AA$)/Si substrates, effects of Ti layer and Pt thickness are studled. Though thickness of the Pt layer 1s 1000$\AA$). oxygen diffusion is not prevented and accelerated by Ti layer actlng for oxygen sink sites durmg furnace annealing. The upper TI layer 1s transformed Into TIOX by oxyen dlffuslon and lower Ti layer Into silicide with in-diffused Pt. The formation of TiOx layer seems to affect the orlentatton of the PZT layer. Furnace annealed f~lm shows ferroelectr~c and electrical properties wth a remanent polarlzation of 3.3$\mu A /\textrm{cm}^2$, , coerclve fleld of 0.15MV/cm, a=571 (10kHz), leakage current 32.65$\mu A /\textrm{cm}^2$, , breakdown voltage of 0.4OMV/cm.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.1
• /
• pp.157-165
• /
• 2001

We analyzed the electrical characteristics of platinum silicide schottky junction to develope the voltage swing in Integrated Schottky Logic gates, and simulated the characteristics with the programs in this junctions. Simulation programs for analytic characteristics are the Medichi tool for device structure, Matlab for modeling and SUPREM V for fabrication process. The silicide junctions consist of PtSi and variable silicon substrate concentrations in ISL gates. Input parameters for simulation characteristics were the same conditions as process steps of the device farications process. The analitic electrical characteristics were the turn-on voltage, saturation current, ideality factor in forward bias, and has shown the results of breakdown voltage between actual characteristics and simulation characteristics in reverse bias. As a result, the forward turn-on voltage, reverse breakdown voltage, barrier height were decreased but saturation current and ideality factor were increased by substrates increased concentration variations.

• Journal of the Microelectronics and Packaging Society
• /
• v.13 no.4
• /
• pp.27-36
• /
• 2006

We fabricated thermally evaporated 10 nm-Ni/(poly)Si, 10 nm-Ni/l nm-Ir/(poly)Si and 10 nm-Ni/l nm-Pt/(poly)Si films to investigate the thermal stability of nickel monosilicides at the elevated temperatures by rapid annealing them at the temperatures of $300{\sim}1200^{\circ}C$ for 40 seconds. Silicides of 50 nm-thick were formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester was used to examine sheet resistance. A scanning electron microscope and field ion beam were employed for thickness and microstructure evolution characterization. An X-ray diffractometer and an Auger depth profiler were used for phase and composition analysis, respectively. Nickel silicides with platinum have no effect on widening the NiSi stabilization temperature region. Nickel silicides with iridium farmed on single crystal silicon showed a low resistance up to $1200^{\circ}C$ while the ones formed on polycrystalline silicon substrate showed low resistance up to $850^{\circ}C$. The grain boundary diffusion and agglomeration of silicides lowered the NiSi stable temperature with polycrystalline silicon substrates. Our result implies that our newly proposed Ir added NiSi process may widen the thermal process window for nano CMOS process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.6
• /
• pp.462-465
• /
• 2009

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method, The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than 10), Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.80-81
• /
• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.