• 한국세라믹학회지
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• 제54권6호
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• pp.506-510
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• 2017

One of the characteristics of polycrystalline graphene that determines its material properties is grain size. Mechanical properties such as Young's modulus, yield strain and tensile strength depend on the grain size and show a reverse Hall-Petch effect at small grain size limit for some properties under certain conditions. While there is agreement on the grain size effect for Young's modulus and yield strain, certain MD simulations have led to disagreement for tensile strength. Song et al. showed a decreasing behavior for tensile strength, that is, a pseudo Hall-Petch effect for the small grain size domain up to 5 nm. On the other hand, Sha et al. showed an increasing behavior, a reverse Hall-Petch effect, for grain size domain up to 10 nm. Mortazavi et al. also showed results similar to those of Sha et al. We suspect that the main difference of these two inconsistent results is due to the different modeling. The modeling of polycrystalline graphene with regular size and (hexagonal) shape shows the pseudo Hall-Petch effect, while the modeling with random size and shape shows the reverse Hall-Petch effect. Therefore, this study is conducted to confirm that different modeling is the main reason for the different behavior of tensile strength of the polycrystalline structures. We conducted MD simulations with models derived from the Voronoi tessellation for two types of grain size distributions. One type is grains of relatively similar sizes; the other is grains of random sizes. We found that the pseudo Hall-Petch effect and the reverse Hall-Petch effect of tensile strength were consistently shown for the two different models. We suspect that this result comes from the different crack paths, which are related to the grain patterns in the models.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권6호
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• pp.403-408
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• 2005

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random This paper proposes and presents a new efficient network architecture for Reflective Memory System (RMS). A time to copy shared-data among nodes effects critically on the entire performance of the RMS. In this paper, the recent researches about the RMS are investigated and compared. The device named Topology Conversion Switch(TCS) is introduced to realize the proposed network architecture. One of the RMS based industrial control networks, Ethernet based Real-time Control Network (ERCnet), is adopted to evaluate the performance of the proposed network architecture for RMS.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권6호
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• Fibers and Polymers
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• 제5권3호
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• pp.245-251
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• 2004

Poly(trimethylene terephthalate-co-trimethylene 2,6-naphthalate)s (P(TT-co-TN)s) with various copolymer composition were synthesized, and their chain structure, thermal property and crystalline structure were investigated by using $^1$H-NMR spectroscopy, differential scanning calorimetry (DSC) and wide-angle X-ray diffraction (WAXD), respectively. It was found from sequence analysis that all the P(TT-co-TN) copolymers synthesized have a statistical random distribution of TT and TN units. It was also observed from DSC thermograms that the glass transition temperature increases linearly with increasing the TN comonomer content, whereas the melting temperature of copolymer decreases with increasing the corresponding comonomer content in respective PTT- and PTN-based copolymer, showing pseudo-eutectic melting behavior. All the samples melt-crystallized isothermally except for P(TT-co-66 mol % TN) exhibit multiple melting endotherms and clear X-ray diffraction patterns. The multiple melting behavior originates from the dual lamellar population and/or the melting-recrystallization-remelting. The X-ray diffraction patterns are largely divided into two classes depending on the copolymer composition, i.e., PTT and PTN $\beta$-form diffraction patterns, without exhibiting cocrystallization.

• 한국정보처리학회논문지
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• 제5권9호
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• pp.2378-2387
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• 1998

본 논문에서는 VLSI 회로의 내장 자체 테스트(Built-In Self-Test)를 위한 효율적인 공간 응답 압축기의 설계 방식을 제안한다. 제안하는 공간 압축기의 설계 방식은 테스트 대상 회로의 구조와는 독립적으로 적용할 수 있다. 기존의 공간 응답 압축기는 하드웨어 오버헤드(hardware overheads)가 크고, 고장 응답을 비고장 응답으로 변환시키는 에일리어싱(aliasing)에 의해 고장 검출률(fault coverage)을 감소시켰으나, 제안하는 방식에 의해 설계된 공간 응답 압축기는 기존의 방법에 비해 하드웨어 오버헤드가 작고, 고장 검출률을 감소시키지 않는다. 또한, 제안하는 방식은 일반적인 N-입력 논리 게이트로 확장이 가능하여 테스트 대상 회로의 출력 시퀸스에 따른 가장 효율적인 공간 응답 압축기를 설계할 수 있다. 제안한 설계 방식은 SUN SPARC Workstation 상에서 C 언어를 사용하여 구현하며, ISCAS'85 벤치마크 회로를 대상으로 선형 피드백 시프트 레지스터(Linear Feedback Shift Registers)에 의해 생성된 의사 랜덤(pseudo random)패턴을 입력원으로 사용하여 시뮬레이션을 수행하므로써 그 타당성과 효율성을 입증한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.594-607
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• 2013

A new efficient analytical eye-diagram determination technique for coupled interconnect lines is presented. Two coupled lines are decoupled into isolated eigen modes; bit blocks for coupled lines, which are defined as a block of consecutive bits, are then represented with decoupled modes. The crosstalk effects within the bit blocks are taken into account. Thereby, the crucial input bit patterns for the worst case eye-diagram determination are modeled mathematically, including inter-symbol interference (ISI). The proposed technique shows excellent agreement with the SPICE-based simulation. Furthermore, it is very computation-time-efficient in the order of magnitude, compared with the SPICE simulation, which requires numerous pseudo-random bit sequence (PRBS) input signals.

• 전자공학회논문지C
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• 제34C권9호
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• pp.53-60
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• 1997

In this paper, an efficient BILBO(named EBILBO) is proposed for batch testing application when a BIST (built-in self test) circuit is implemented on ASIC. In a large and complex circuit, the proposed algorithm of batch testing has one pin-count that can easily control 4 test modes in the normal speed of circuit operation. For the implementation of the BIST cifcuit, the test patern needed is generated by PRTPG(pseudo-random test pattern generator) and the ouput is observed by proposed algorithm is easily modified, such as the modelling of test pattern genration, signature EBILBO area and performance of the implemented BIST are evaluated using ISCAS89 benchmark circuits. As a resutl, in a circuit above 600 gates, it is confirmed that test patterns are genrated flexibly about 500K as EBILBO area is 59%, and the range of fault coverage is from 88.3% to 100%. And the optimized operation frequency of EBILBO designed and the area are 50MHz and 150K respectively. On the BIST circit of the proposed batch testing, the test mode of EBILBO is able to execute as realtime that has te number of s$\^$+/n$\^$+/(2s/2p-1) clocks simultaneously with the normal mode of circuit operation. Also the proposed algorithm is made of the library with VHDL coding thus, it will be widely applied to DFT (design for testability) that satisfies the design and test field.

• 정보보호학회논문지
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• 제14권6호
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• pp.25-30
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• 2004

최대길이를 갖는 선형 90/150 셀룰라 오토마타(CA)가 패턴생성, 신호분석, 암호, 오류정정 부호에 응용되면서 n차 원시다항식을 특성다항식으로 갖는 선형 CA에 관한 연구가 활발하게 이루어지고 있다. 본 논문은 최대길이를 갖는 다양한 셀룰라 오토마타의 효과적인 생성방법을 제안한다. 특성다항식이 n차 원시다항식인 선형이며 최대길이를 갖는 CA(MLCA)로부터 유도된 여원 CA가 MLCA임을 밝히며 여원 MLCA의 여러 가지 성질들을 분석한다 또한 n-셀 MLCA를 ${\phi}(2^{n}-1)2^{n+1}$/n.개 생성할 수 있음을 보인다.

• 한국전자통신학회논문지
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• 제15권6호
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• pp.1105-1112
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• 2020

1차원 3-이웃 셀룰라 오토마타(Cellular Automata, 이하 CA) 기반의 의사난수 생성기는 시스템의 성능을 평가하기 위한 테스트 패턴 생성과 암호 시스템의 키수열 생성기 등에 많이 응용되고 있다. 본 논문에서는 더 복잡하고 혼돈스러운 수열을 생성할 수 있는 CA기반의 키 수열 생성기를 설계하기 위해 각 셀의 상태전이에 영향을 주는 이웃을 5개로 확장한 1차원 대칭 5-이웃 CA에 대해 연구한다. 특히 대칭 5-이웃 CA를 합성하기 위해 Krylov 행렬을 이용하는 대수적인 방법과 Cho et al.의 알고리즘을 기반으로 한 1차원 n셀 대칭 5-이웃 CA 합성 알고리즘을 제안한다.

• 대한전자공학회논문지SD
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• 제45권6호
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• pp.43-48
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• 2008

일반적으로 자체 테스트 동작은 입력 벡터들 사이에 상호 연관성이 없기 때문에 더 많은 전력을 소비하는 것으로 알려져 있다. 이러한 점은 회로에 손상을 유발할 뿐 아니라 배터리 수명에도 악영향을 미치기 때문에 반드시 해결되어야 할 과제 중 하나이다. 이를 위해 본 논문에서는 새로운 방식의 BIST(Built-In Self Test) 구조를 제안하여 테스트 동작에서의 천이를 감소시키고, 이를 통해 전력소모를 줄이고자 한다. 제안하는 구조에서는 LFSR(Linear Feedback Shift Register)을 통해 생성되는 pseudo-random 테스트 벡터가 스캔 경로로 들어가기 전에 3 bit씩 모아 더 적은 천이를 가지는 4 bit의 패턴으로 변형한다. 이러한 변형과 그에 대한 복원 과정은 기존의 스캔 BIST 구조에서 Bit Generator와 Bit Dropper라는 모듈을 추가하여 간단히 구현하였다. 제안하는 구조를 ISCAS'89 benchmark 회로에 적용한 결과 약 62%의 천이 감소를 확인하였고 이를 통해 제안하는 구조의 효율성을 검증하였다.