• 제어로봇시스템학회:학술대회논문집
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• 1992.10b
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• pp.479-484
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• 1992

The resolved motion rate control (RMRC) is converting to Joint space trajectory from given Cartesian space trajectory. The RMRC requires the inverse of Jacobian matrix. Since the Jacobian matrix of the redundant robot is generally not square, the pseudo-inverse must be introduced. However the pseudo-inverse is not easy to be implemented on a digital computer in real time as well as mathematically complex. In this paper, a simple fuzzy resolved motion rate control (FRMRC) that can replace the RMRC using pseudo-inverse of Jacobian is proposed. The proposed FRMRC with appropriate fuzzy rules, membership functions and reasoning method can solve the mapping problem between the spaces without complexity. The mapped Joint space trajectory is sufficiently accurate so that it can be directly used to control redundant manipulators. Simulation results verify the efficiency of the proposed idea.

• ETRI Journal
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• v.35 no.4
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• pp.610-616
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• 2013

This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology. The RFID logic circuit generates 16-bit code programmed in read-only memory. All circuits are implemented in a pseudo-CMOS logic style using transparent a-IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300-nm to 800-nm wavelength. The RFID logic chip generates Manchester-encoded 16-bit data with a 3.2-kHz clock frequency and consumes 170 ${\mu}W$ at $V_{DD}=6$ V. It employs 222 transistors and occupies a chip area of 5.85 $mm^2$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.165-171
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• 1996

A noncoherent full-digital PN(pseudo noise) code acquisition/tracking loop has been presetned and implemented in FPGA for the CDMA band-limited direct-sequence spread-spectrum (DS-SS) signals. It employs a simple decimator to control of local PN code phase to lower the hardware cost, and a second order loop to enable the more accurate tracking. The proposed acquisition/tracking loop has been designed in RTL-level VHDL, synthesized into logic gates using the design analyzer of synopsys software, implemented in an ALTERA FPGA chip, and tested. The number of logic gates used in the implemented FPGA chip is around 7000. The functionality has been verified using a PC interface circuitry and a logic analyzer.

• ETRI Journal
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• v.36 no.6
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• pp.942-952
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• 2014

This paper presents a novel test point insertion (TPI) method for a pseudo-random built-in self-test (BIST) to reduce the area overhead. Recently, a new TPI method for BISTs was proposed that tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving control points. The replacement rule used in a previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip-flops. This paper proposes a logic cone analysis-based TPI approach to overcome the limitations. Logic cone analysis is performed to find candidate functional flop-flops for replacing dedicated flip-flops. Experimental results indicate that the proposed method reduces the test point area overhead significantly with minimal loss of testability by replacing the dedicated flip-flops.

• Korean Journal of Logic
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• v.19 no.1
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• pp.107-126
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• 2016

This paper deals with Kripke-style semantics for weakening-free non-commutative fuzzy logics. As an example, we consider an algebraic Kripke-style semantics for an extension of the pseudo-uninorm based fuzzy logic HpsUL, $CnHpsUL^*$. For this, first, we recall the system $CnHpsUL^*$, define its corresponding algebraic structures $CnHpsUL^*$-algebras, and algebraic completeness results for it. We next introduce a Kripke-style semantics for $CnHpsUL^*$, and connect it with algebraic semantics.

• International Journal of Contents
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• v.5 no.2
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• pp.53-58
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• 2009

This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.188-202
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• 1996

In this paper, we propose a symmetrical pseudo faulty processing elements genration technique to improve the overall reliability of arrays with fixed hardware resources on the fault tolerant VLSI arrays based on single-track switches. We have analyzed the reliability of fault tolerant VLSI arrays and designed control logic for real-tiem reconfiguration. Applying this technique to reconfiguration of VLSI 2-D arrays, we have found that the proposed scheme achieves a higher reliability than the previus methods of similar condition. And we have found that the results of reliability analyzed by mathematic computation are very close to simulated ones. Furthermore, the time overhead for reconfiguration is independent of the array size because the control for reconfiguration is distributively executed by each processing elements. And the proposed scheme has an advantage which maintained properties of VLSI arrays by keeping the locality of interconnections as high as possible even after the reconfiguration.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1442-1447
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• 1990

In this paper we propose the search algorithm of the boundary nodes that defined as the circuit segmentation when CUT is tested by pseudo-exhaustive testing. The algorithm treats the testability values of the nodes in CUT as the population composed of teh raw data, and after examines the level of significance a and then estimate the confidence interval of teh testability values. Thus One can easily searched the c9oundary nodes and PO of sub circuits. The proposed algorithm has been implemented under UNIX OS with C-language, applied to the combinational logic CUT. As a result, it is shown that the pseudo-exhaustive test patterns are least generated when \ulcornerhas 0.786. We confirmed that the rate of test pattern is 1.22%, compared with exhaustive test.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.50.6-50
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• 2001

This paper deals with a design of nonlinear glide slope capture logic using dynamic model inversion in singular perturbation, which is applicable to the autolanding in ILS. Aircraft dynamics are separated into the fast time-scale variables, related with the inner-loop design, and the slow time-scale variables, related with the outer-loop design. It is assumed that the aircraft starts landing at 1000ft of altitude, -2.5deg of flight path angle, and 250ft/sec of velocity. In the outer-loop design, commands of altitude and velocity are selected and thereby the pseudo-controls of power level and pitch rate are determined. Also the elevator input to the aircraft is determined in the inner-loop design. The final design is evaluated in 6 DOF simulation model of the associated aircraft, in which the actuator models are not included. The results show the satisfactory autolanding ...

• Broadcasting and Media Magazine
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• v.3 no.1
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• pp.13-19
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• 1998

본 논고에서는 VHDL ASIC 설계 기술을 사용하여 Chip을 설계할 때에 필요한 사항과 방법 그리고 실제 사용 예로써 MPEG 오디오 Chip의 설계와 구현에 관하여 기술한 것이다. VHDL을 이용한 설계의 흐름도로부터 실제 설계를 위한 방법까지 기술하였고 알고리듬의 최적화를 위한 방법과 그 예를 보이고 있다. 또 Gate를 이용한 Logic Level설계에 익숙하지 않은 설계자도 쉽고 빠르게 사용할 수 있는 VHDL설계 기술을 이용하여 MPEG-2 의 2 채널 모드까지 지원하는 Chip의 설계에 관하여 기술한다. 특히 합성 필터를 설계할때 계산량을 줄이고 RAM의 크기를 줄일 수 있도록 효율적인 구현을 위해 구조를 설계하였으며 ROM에 저장될 합성 필터 계수의 수를 줄이기 위해 노력하였다. 또 합성 필터의 Control을 위하여 Pseudo_RISC개념을 사용하였다.